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公开(公告)号：US07592275B2
公开(公告)日：2009-09-22
申请号：US11940113
申请日：2007-11-14
IPC分类号： H01L21/00
CPC分类号： H01L29/66757 , C23C16/4404 , H01L21/67063 , H01L27/12
摘要： A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a substrate having source and drain electrodes formed thereon in the processing chamber. Additional steps include doping the source and drain electrodes with P, and forming an a-Si layer and a gate insulating film in the processing chamber. Furthermore, an apparatus is provided for manufacturing an active matrix device including a top gate type TFT having the inner surface of the processing chamber coated with the oxide film.
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公开(公告)号：US06600196B2
公开(公告)日：2003-07-29
申请号：US09761030
申请日：2001-01-16
IPC分类号： H01L2701
CPC分类号： H01L29/78696 , H01L29/78609 , H01L29/78633
摘要： The present invention relates to minimizing a leakage current in a floating island portion formed in a thin film transistor. More specifically, the present invention is directed to a thin film transistor including: a source electrode 14 and a drain electrode 15 disposed above an insulating substrate 11 at a predetermined interval; an s-Si film 16 disposed in relation to the source electrode 14 and drain electrode 15; a gate insulating film 17 overlapping the a-Si film 16; and a gate electrode 18 overlapping the gate insulating film 17, in which the a-Si film 16 is disposed between the source electrode 14 and the drain electrode 15 and has a floating island portion 20 above which or beneath which the gate electrode 18 is not formed, and boron ions are implanted into this portion to form a boron-ion-implanted region 19.
摘要翻译： 本发明涉及使形成在薄膜晶体管中的浮岛部分中的漏电流最小化。 更具体地，本发明涉及一种薄膜晶体管，其包括：源极电极14和漏电极15，其以预定间隔设置在绝缘基板11上方; 相对于源电极14和漏电极15设置的s-Si膜16; 与a-Si膜16重叠的栅极绝缘膜17; 以及与栅极绝缘膜17重叠的栅电极18，其中a-Si膜16设置在源电极14和漏电极15之间，并且在栅极电极18之上或之下具有浮岛区20 并将硼离子注入该部分以形成硼离子注入区19。
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3.发明授权Thin film transistor, liquid crystal display panel, and method of manufacturing thin film transistor 有权薄膜晶体管，液晶显示面板以及制造薄膜晶体管的方法公开(公告)号：US06816209B2
公开(公告)日：2004-11-09
申请号：US10617964
申请日：2003-07-11
IPC分类号： G02F1136
CPC分类号： G02F1/136209 , H01L27/124 , H01L29/78633
摘要： The present invention reduces the number of necessary steps in a thin-film-transistor manufacturing process and prevents an abnormal potential from being generated due to a leak current from another data line. More particularly, the present invention is directed to a thin film transistor comprising a gate electrode 30 disposed on a predetermined substrate and formed in a predetermined pattern, a semiconductor layer formed correspondingly to patterning of the gate electrode 30, a pixel electrode 25 interposed by the semiconductor layer, and a signal electrode 26 interposed by the semiconductor layer and disposed at a predetermined interval from the pixel electrode 25, in which the signal electrode 26 is disposed at such a position where the signal electrode prevents crosstalk running from adjacent signal lines 32b and 32c to the pixel electrode 25 via the semiconductor layer.
摘要翻译： 本发明减少薄膜晶体管制造工艺中的必要步骤的数量，并且防止由于来自另一数据线的漏电流而产生异常电位。更具体地，本发明涉及一种薄膜晶体管，其包括 设置在预定基板上并以预定图案形成的栅电极30，对应于栅电极30的图形形成的半导体层，由半导体层插入的像素电极25和由半导体层插入的信号电极26，以及 以与信号电极26配置在信号电极防止从相邻的信号线32b，32c到像素电极25的串扰通过半导体层的位置的像素电极25隔开规定的间隔配置。
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4.发明申请METHOD AND APPARATUS FOR MANUFACTURING ACTIVE MATRIX DEVICE INCLUDING TOP GATE TYPE TFT 有权用于制造包括顶栅型TFT的有源矩阵器件的方法和装置公开(公告)号：US20080230007A1
公开(公告)日：2008-09-25
申请号：US11940113
申请日：2007-11-14
IPC分类号： C23C16/00
CPC分类号： H01L29/66757 , C23C16/4404 , H01L21/67063 , H01L27/12
摘要： A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a substrate having source and drain electrodes formed thereon in the processing chamber. Additional steps include doping the source and drain electrodes with P, and forming an a-Si layer and a gate insulating film in the processing chamber. Furthermore, an apparatus is provided for manufacturing an active matrix device including a top gate type TFT having the inner surface of the processing chamber coated with the oxide film.
摘要翻译： 提供了一种用于制造包括顶栅型TFT的有源矩阵器件的方法和装置。 顶栅型TFT的制造工艺包括以下步骤：在CVD处理室的内壁上形成氧化物膜，并且将其上形成有源极和漏极的衬底布置在处理室中。 附加步骤包括用P掺杂源极和漏极，并在处理室中形成a-Si层和栅极绝缘膜。 此外，提供一种用于制造有源矩阵器件的装置，其包括具有涂覆有氧化物膜的处理室的内表面的顶栅型TFT。
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5.发明授权公开(公告)号：US06525341B1
公开(公告)日：2003-02-25
申请号：US09620116
申请日：2000-07-20
IPC分类号： H01L2904
CPC分类号： H01L29/78696 , H01L29/66765 , H01L29/78669
摘要： The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.
摘要翻译： 本发明提高了在薄膜晶体管中生长a-Si膜的生产率，并获得优异的薄膜晶体管特性。 更具体地，公开了一种薄膜晶体管，其中非晶硅膜2，栅极绝缘膜3和栅电极依次层叠在绝缘基板1上。非晶硅膜2包括低缺陷密度非晶硅层5 以低沉积速率形成，并以高于低缺陷密度非晶硅层5的沉积速率形成沉积速率非晶硅层6.非晶硅膜2中的低缺陷密度非晶硅层5是 生长在更靠近绝缘基板1的地方，并且高沉积速率非晶硅层6生长得更靠近栅极绝缘膜3。
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6.发明授权Method and apparatus for manufacturing active matrix device including top gate type TFT 有权包括顶栅型TFT的有源矩阵器件的制造方法和装置公开(公告)号：US07344927B2
公开(公告)日：2008-03-18
申请号：US09681643
申请日：2001-05-15
IPC分类号： H01L21/00
CPC分类号： H01L29/66757 , C23C16/4404 , H01L21/67063 , H01L27/12
摘要： A method and an apparatus are provided for manufacturing an active matrix device including a top gate type TFT. A manufacturing process of the top gate type TFT includes the steps of forming an oxide film on the inner wall of a CVD processing chamber and arranging a substrate having source and drain electrodes formed thereon in the processing chamber. Additional steps include doping the source and drain electrodes with P, and forming an a-Si layer and a gate insulating film in the processing chamber. Furthermore, an apparatus is provided for manufacturing an active matrix device including a top gate type TFT having the inner surface of the processing chamber coated with the oxide film.
摘要翻译： 提供了一种用于制造包括顶栅型TFT的有源矩阵器件的方法和装置。 顶栅型TFT的制造工艺包括以下步骤：在CVD处理室的内壁上形成氧化物膜，并且将其上形成有源极和漏极的衬底布置在处理室中。 附加步骤包括用P掺杂源极和漏极，并在处理室中形成a-Si层和栅极绝缘膜。 此外，提供一种用于制造有源矩阵器件的装置，其包括具有涂覆有氧化物膜的处理室的内表面的顶栅型TFT。
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7.发明授权Thin film transistor, liquid crystal display device and method of fabricating the thin film transistor 有权薄膜晶体管，液晶显示装置及制造薄膜晶体管的方法公开(公告)号：US07115448B2
公开(公告)日：2006-10-03
申请号：US10833754
申请日：2004-04-28
CPC分类号： H01L29/78696 , H01L29/66765 , H01L29/78669
摘要： The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.
摘要翻译： 本发明提高了在薄膜晶体管中生长a-Si膜的生产率，并获得优异的薄膜晶体管特性。 更具体地，公开了一种薄膜晶体管，其中非晶硅膜2，栅极绝缘膜3和栅电极依次层叠在绝缘基板1上。 非晶硅膜2包括以低沉积速率形成的低缺陷密度非晶硅层5和以低于低缺陷密度非晶硅层5的沉积速率形成的沉积速率非晶硅层6。 非晶硅膜2中的低缺陷密度非晶硅层5生长在更靠近绝缘基板1的地方，并且高沉积速率非晶硅层6生长得更靠近栅极绝缘膜3。
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8.发明授权Thin film transistor, liquid crystal display panel, and method of manufacturing thin film transistor 有权薄膜晶体管，液晶显示面板以及制造薄膜晶体管的方法公开(公告)号：US06801266B1
公开(公告)日：2004-10-05
申请号：US09614767
申请日：2000-07-12
IPC分类号： G02F1136
CPC分类号： G02F1/136209 , H01L27/124 , H01L29/78633
摘要： The present invention reduces the number of necessary steps in a thin-film-transistor manufacturing process and prevents an abnormal potential from being generated due to a leakage current from another signal line. A thin film transistor comprises a gate electrode 30 disposed on a predetermined substrate and formed in a predetermined pattern, a semiconductor layer 27 formed correspondingly to patterning of the gate electrode 30, a pixel electrode 25 interposed by the semiconductor layer, and a signal electrode 26 interposed by the semiconductor layer and disposed at a predetermined interval from the pixel electrode 25, in which the signal electrode 26 is disposed at such a position where the signal electrode prevents crosstalk leakage current flowing from adjacent signal lines 32b and 32c to the pixel electrode 25 via the semiconductor layer.
摘要翻译： 本发明减少薄膜晶体管制造工艺中必要的步骤数量，并且防止由于来自另一信号线的泄漏电流而产生异常电位。 薄膜晶体管包括设置在预定衬底上并以预定图案形成的栅电极30，对应于栅电极30的图形形成的半导体层27，由半导体层插入的像素电极25和信号电极26 由半导体层插入并且以像素电极25预定间隔设置，其中信号电极26设置在信号电极防止从相邻信号线32b和32c流到像素电极25的串扰泄漏电流的位置 通过半导体层。
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9.发明授权Liquid crystal display device having a thin film transistor element including an amorphous film containing a low-defect density layer and a high-defect densisty layer 有权具有薄膜晶体管元件的液晶显示装置，该薄膜晶体管元件包括含有低缺陷密度层和高缺陷密度层的非晶膜公开(公告)号：US06753550B2
公开(公告)日：2004-06-22
申请号：US10331699
申请日：2002-12-30
IPC分类号： H01L2904
CPC分类号： H01L29/78696 , H01L29/66765 , H01L29/78669
摘要： The present invention improves a productivity in growing an a-Si film in a thin film transistor and to obtain an excellent thin film transistor characteristic. More specifically, disclosed is a thin film transistor in which an amorphous silicon film 2, a gate insulating film 3 and a gate electrode are sequentially stacked on an insulating substrate 1. The amorphous silicon film 2 includes a low defect-density amorphous silicon layer 5 formed at a low deposition rate and a high deposition rate amorphous silicon layer 6 formed at a deposition rate higher than that of the low defect-density amorphous silicon layer 5. The low defect-density amorphous silicon layer 5 in the amorphous silicon film 2 is grown closer to the insulating substrate 1, and the high deposition rate amorphous silicon layer 6 is grown closer to the gate insulating film 3.
摘要翻译： 本发明提高了在薄膜晶体管中生长a-Si膜的生产率，并获得优异的薄膜晶体管特性。 更具体地，公开了一种薄膜晶体管，其中非晶硅膜2，栅极绝缘膜3和栅电极依次层叠在绝缘基板1上。非晶硅膜2包括低缺陷密度非晶硅层5 以低沉积速率形成，并以高于低缺陷密度非晶硅层5的沉积速率形成沉积速率非晶硅层6.非晶硅膜2中的低缺陷密度非晶硅层5是 生长在更靠近绝缘基板1的地方，并且高沉积速率非晶硅层6生长得更靠近栅极绝缘膜3。
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10.发明授权Top gate TFT structure having light shielding layer and method to fabricate the same 有权具有遮光层的顶栅TFT结构及其制造方法公开(公告)号：US06608658B1
公开(公告)日：2003-08-19
申请号：US09620114
申请日：2000-07-20
IPC分类号： G02F11333
CPC分类号： H01L27/1288 , G02F1/1362 , H01L27/1214 , H01L29/66757 , H01L29/78633
摘要： The present invention provides a method of fabricating a TFT structure by two masking processes. More specifically, a light shielding layer and an interlayer insulating layer are sequentially formed on a substrate, and then source/drain electrodes are formed on the interlayer insulating layer (a first masking step). A semiconductor layer, a gate insulating layer and a gate metal layer are sequentially formed so as to cover the source/drain electrodes, and a gate electrode is formed in a second masking step. Subsequently, the gate insulating layer and the semiconductor layer are etched, and the interlayer insulating layer and the light shielding layer, which are disposed under the source/drain electrodes, are etched using the source/drain electrodes as a mask, thus obtaining a top gate TFT structure. When the interlayer insulating layer and the gate insulating layer are made of an insulating material containing SiOX and SiNX as a main component, the gate insulating layer and the semiconductor layer are naturally over-etched more than the interlayer insulating layer and the light shielding layer by plasma-etching with mixed gas of CF4 and hydrogen, thus obtaining a TFT structure with a high reliability, which is free from a problem of occurrence of photo-induced leak current.
摘要翻译： 本发明提供了一种通过两个屏蔽工艺制造TFT结构的方法。 更具体地，在衬底上依次形成遮光层和层间绝缘层，然后在层间绝缘层上形成源极/漏极（第一掩蔽步骤）。 顺序地形成半导体层，栅极绝缘层和栅极金属层以覆盖源极/漏极，并且在第二掩蔽步骤中形成栅电极。 随后，蚀刻栅极绝缘层和半导体层，并且使用源极/漏极作为掩模蚀刻设置在源极/漏极下方的层间绝缘层和遮光层，从而获得顶部 门TFT结构。 当层间绝缘层和栅极绝缘层由含有SiOX和SiNX作为主要成分的绝缘材料制成时，栅绝缘层和半导体层自然地比层间绝缘层和遮光层过度蚀刻 用CF4和氢气的混合气体进行等离子体蚀刻，从而获得具有高可靠性的TFT结构，其没有发生光诱导漏电流的问题。
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