公开(公告)号：US20120068763A1

公开(公告)日：2012-03-22

申请号：US13233694

申请日：2011-09-15

申请人： Takeshi HIOKA ,  Daisaburo Takashima

发明人： Takeshi HIOKA ,  Daisaburo Takashima

IPC分类号： H01L25/18

CPC分类号： G11C16/32 ,  G11C16/30

摘要： According to one embodiment, a semiconductor integrated circuit device includes an output circuit which includes an inverter having a first transistor and a second transistor whose current paths are series-connected between a first power supply voltage and a second power supply voltage, a first diode circuit one end of which is connected to the first power supply voltage, and the other end of which is connected to a control terminal of the first transistor, and an adjustment circuit which forms a current path for discharging a charge of the control terminal of the first transistor to the second power supply voltage when an input clock is at a first level.

摘要翻译： 根据一个实施例，半导体集成电路器件包括输出电路，该输出电路包括具有第一晶体管的反相器和电流路径串联连接在第一电源电压和第二电源电压之间的第二晶体管，第一二极管电路 其一端连接到第一电源电压，另一端连接到第一晶体管的控制端，以及调节电路，形成用于对第一晶体管的控制端的电荷进行放电的电流通路 当输入时钟处于第一电平时，晶体管到第二电源电压。

公开(公告)号：US20110234306A1

公开(公告)日：2011-09-29

申请号：US13047088

申请日：2011-03-14

申请人： Takeshi HIOKA ,  Daisaburo Takashima

发明人： Takeshi HIOKA ,  Daisaburo Takashima

IPC分类号： G05F1/10

CPC分类号： H02M3/07

摘要： In a booster, a first transistor of a second conduction-type is formed on a first conduction-type substrate and connected to between a voltage-source and an output so that the first transistor functions as a diode. A first capacitor is connected to a first node of the first transistor on a voltage-source side, and transmits a first clock to the first node. A second transistor of the first conduction-type is connected to a second node of the first transistor on an output side to receive the first clock. A second capacitor is connected to the second node and transmits a second clock having an opposite phase of the first clock to the second node. The first transistor transfers the first node's voltage stepped up by the first clock to the second node. The second transistor transfers the second node's voltage stepped up by the second clock to an output side.

摘要翻译： 在升压器中，在第一导电型衬底上形成第二导电类型的第一晶体管，并连接到电压源和输出端之间，使得第一晶体管用作二极管。 第一电容器连接到电压源侧的第一晶体管的第一节点，并将第一时钟发送到第一节点。 第一导电类型的第二晶体管在输出侧连接到第一晶体管的第二节点以接收第一时钟。 第二电容器连接到第二节点并将具有第一时钟的相反相位的第二时钟发送到第二节点。 第一晶体管将第一节点的电压向第二个节点转移。 第二晶体管将第二节点的电压递增到第二时钟输出端。

公开(公告)号：US20100237933A1

公开(公告)日：2010-09-23

申请号：US12729169

申请日：2010-03-22

申请人： Takeshi HIOKA ,  Ryu OGIWARA ,  Daisaburo TAKASHIMA

发明人： Takeshi HIOKA ,  Ryu OGIWARA ,  Daisaburo TAKASHIMA

IPC分类号： G05F1/10

CPC分类号： G05F1/561

摘要： A current supply circuit according to an embodiment of the present invention includes an operational amplifier having first and second input terminals and an output terminal, a transistor having a control terminal connected to the output terminal of the operational amplifier, and having first and second main terminals, a first resistance arranged between the first input terminal of the operational amplifier and the first main terminal of the transistor, a second resistance arranged between a predetermined node and a ground line, the predetermined node being between the first input terminal of the operational amplifier and the first resistance, first to Nth transistors, each of which has a control terminal connected to the control terminal or the second main terminal of the transistor, and has a main terminal outputting a current, where N is an integer of two or larger, and first to Nth switching transistors, each of which has a main terminal, the main terminals of the first to Nth switching transistors being respectively connected to the main terminals of the first to Nth transistors, a pulse width of a signal provided to a control terminal of the respective first to Nth switching transistors being set to be constant regardless of a pulse frequency of the signal.

摘要翻译： 根据本发明的实施例的电流供应电路包括具有第一和第二输入端和输出端的运算放大器，具有连接到运算放大器的输出端的控制端的晶体管，并具有第一和第二主端 布置在运算放大器的第一输入端和晶体管的第一主端之间的第一电阻，布置在预定节点和地线之间的第二电阻，所述预定节点位于运算放大器的第一输入端和 第一电阻，第一至第N晶体管，每个具有连接到晶体管的控制端子或第二主端子的控制端子，并且具有输出电流的主端子，其中N为2或更大的整数，以及 第一至第N开关晶体管，其中每个具有主端子，主端子为第一至第N开关 正弦晶体管分别连接到第一至第N晶体管的主端子，提供给相应的第一至第N开关晶体管的控制端的信号的脉冲宽度被设置为恒定，而与信号的脉冲频率无关。

公开(公告)号：US20130113080A1

公开(公告)日：2013-05-09

申请号：US13671077

申请日：2012-11-07

申请人： Takeshi HIOKA ,  Yoshiaki Fukuzumi

发明人： Takeshi HIOKA ,  Yoshiaki Fukuzumi

IPC分类号： H01L27/06 ,  H01L21/02

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L28/88

摘要： A non-volatile semiconductor storage device contains a memory cell region, a first electrode, and a second electrode. The memory cell region is formed on a substrate and comprises multiple memory cells stacked on the substrate as part of memory strings. Multiple first conductive layers are laminated on the substrate. The first electrode functions as an electrode at one side of a capacitive component and comprises multiple conductive layers stacked on the substrate and separated horizontally from stacked conductive layers of the second electrode which is disposed at a side of the capacitive component opposite the first electrode.

摘要翻译： 非易失性半导体存储装置包含存储单元区域，第一电极和第二电极。 存储单元区域形成在衬底上并且包括作为存储器串的一部分堆叠在衬底上的多个存储器单元。 多个第一导电层层叠在基板上。 第一电极用作电容部件一侧的电极，并且包括层叠在基板上的多个导电层，并且与设置在与第一电极相对的电容部件侧的第二电极的层叠导电层水平分离。

公开(公告)号：US20130242651A1

公开(公告)日：2013-09-19

申请号：US13600936

申请日：2012-08-31

申请人： Takeshi HIOKA

发明人： Takeshi HIOKA

IPC分类号： G11C11/40

CPC分类号： G11C11/40 ,  G11C16/0483 ,  G11C16/30 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/7926

摘要： A first capacitor includes a plurality of first conductive layers and second conductive layers. The first conductive layers function as a first electrode of the first capacitor, the second conductive layers function as a second electrode of the first capacitor. The first conductive layers and the second conductive layers are arranged alternately in the direction substantially perpendicular to a semiconductor substrate. A control circuit is configured to control a voltage applied to each of first conductive layers and the second conductive layers according to voltages of gates of a plurality of memory transistors, thereby changing a capacitance of the first capacitor.

摘要翻译： 第一电容器包括多个第一导电层和第二导电层。 第一导电层用作第一电容器的第一电极，第二导电层用作第一电容器的第二电极。 第一导电层和第二导电层在基本上垂直于半导体衬底的方向上交替布置。 控制电路被配置为根据多个存储晶体管的栅极的电压来控制施加到第一导电层和第二导电层中的每一个的电压，从而改变第一电容器的电容。