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    Semiconductor device having improved trench structure
    5.
    发明授权
    Semiconductor device having improved trench structure 失效
    具有改善的沟槽结构的半导体器件

    公开(公告)号：US06777772B1

    公开(公告)日：2004-08-17

    申请号：US09189870

    申请日：1998-11-12

    申请人： Masatoshi Taya ,  Takio Ohno ,  Naofumi Murata

    发明人： Masatoshi Taya ,  Takio Ohno ,  Naofumi Murata

    IPC分类号： H01L2900

    CPC分类号： H01L21/78

    摘要： Trenches for defining chip areas are formed on the surface of a semiconductor substrate so that outlines of side walls of each of the trenches have recesses or protrusions. Then, a sputtering film is so formed as to be continuous in an area bridging the surface of each of the chip areas and the inside surface of each of the trenches, and the semiconductor substrate is diced along lines outside the trenches.

    摘要翻译： 用于限定芯片区域的沟槽形成在半导体衬底的表面上，使得每个沟槽的侧壁的轮廓具有凹部或突起。 然后，将溅射膜形成为在桥接每个芯片区域的表面和每个沟槽的内表面的区域中连续，并且半导体衬底沿着沟槽外的线切割。

    Method of maufacturing field effect transistor
    6.
    发明授权
    Method of maufacturing field effect transistor 失效
    制造场效应晶体管的方法

    公开(公告)号：US5773347A

    公开(公告)日：1998-06-30

    申请号：US601543

    申请日：1996-02-14

    申请人： Masatoshi Kimura ,  Takio Ohno

    发明人： Masatoshi Kimura ,  Takio Ohno

    IPC分类号： H01L21/28 ,  H01L21/265 ,  H01L21/266 ,  H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L21/335

    CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/66545 ,  Y10S438/902

    摘要： A method of manufacturing a field effect transistor can prevent increase of a sheet resistance of a metal silicide layer formed on a gate electrode. In this method of manufacturing the field effect transistor, gate electrode protective layers are formed on the gate electrodes. Using the gate electrode layers as a mask, impurity is ion-implanted into a semiconductor substrate to form source/drain regions. Thereby, the ion implantation for forming the source/drain regions can be performed without ion-implanting the impurity into top surfaces of the gate electrodes. As a result, increase of a sheet resistance of the metal silicide layer, which is formed on the top surfaces of the gate electrodes, is prevented. The use of rotary implantation and of gate protective layer including a silicon oxide film and an etching stopper layer formed on the oxide film is also disclosed.

    摘要翻译： 制造场效应晶体管的方法可以防止形成在栅电极上的金属硅化物层的薄层电阻增加。 在该场效应晶体管的制造方法中，在栅电极上形成栅电极保护层。 使用栅极电极层作为掩模，将杂质离子注入到半导体衬底中以形成源极/漏极区。 由此，可以在不将杂质离子注入到栅电极的顶面的情况下进行用于形成源极/漏极区域的离子注入。 结果，防止了形成在栅电极的顶表面上的金属硅化物层的薄层电阻的增加。 还公开了使用旋转注入和包括形成在氧化物膜上的氧化硅膜和蚀刻阻挡层的栅极保护层。

    Semiconductor device including a local interconnection between an interconnection layer and an adjoining impurity region
    8.
    发明授权
    Semiconductor device including a local interconnection between an interconnection layer and an adjoining impurity region 失效
    半导体器件包括互连层和相邻杂质区之间的局部互连

    公开(公告)号：US5621232A

    公开(公告)日：1997-04-15

    申请号：US522223

    申请日：1995-09-01

    申请人： Takio Ohno

    发明人： Takio Ohno

    IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/11 ,  H01L29/43 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L21/76889 ,  H01L21/76895 ,  H01L27/11 ,  H01L27/1104 ,  Y10S257/903

    摘要： A p-type silicon substrate is provided at its main surface with n-type impurity regions with a space between each other. A gate electrode is formed on a region between the n-type impurity regions with a gate insulating film therebetween. A titanium silicide layer is formed in a region extending from a surface layer of the gate electrode to a surface layer of the n-type impurity region. The titanium silicide layer forms a local interconnection. A side wall insulating film remains on a side wall of the gate electrode on which the titanium silicide layer is not formed. Thereby, the semiconductor device can have a local interconnection which has high reliability and can be formed easily.

    摘要翻译： 在其主表面上设置有p型硅衬底，其间具有彼此间隔的n型杂质区域。 栅极电极形成在n型杂质区域之间的区域之间，其间具有栅极绝缘膜。 在从栅电极的表面层延伸到n型杂质区的表面层的区域中形成硅化钛层。 硅化钛层形成局部互连。 侧壁绝缘膜保留在其上未形成硅化钛层的栅电极的侧壁上。 因此，半导体器件可以具有高可靠性并且可以容易地形成的局部互连。

    Semiconductor integrated circuit device having static memory cell with CMOS structure
    9.
    发明授权
    Semiconductor integrated circuit device having static memory cell with CMOS structure 失效
    具有CMOS结构的静态存储单元的半导体集成电路器件

    公开(公告)号：US5880503A

    公开(公告)日：1999-03-09

    申请号：US791619

    申请日：1997-01-31

    申请人： Hisashi Matsumoto ,  Takio Ohno

    发明人： Hisashi Matsumoto ,  Takio Ohno

    IPC分类号： H01L21/8234 ,  H01L21/8244 ,  H01L27/088 ,  H01L27/11 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L27/1104 ,  Y10S257/903

    摘要： A titanium silicide (4) covers surfaces of P.sup.+ -type diffusion region (7) and N.sup.+ -type diffusion region (8) to electrically connect the diffusion regions (7, 8) through the titanium silicide (4), and a surface of the titanium silicide (4) is covered with an insulation film (10). A power supply potential applied to a metal wire (2) is thereby applied to an N.sup.+ -type diffusion region (6), an N well (12) and the N.sup.+ -type diffusion region (8) through a contact hole (3) and further supplied for the P.sup.+ -type diffusion region (7) serving as a source region of PMOS transistor through the titanium silicide (4). That eliminates the need for providing any contact for supplying the diffusion regions 7 and 8 with the power supply potential to attain reduction in layout size, while preventing a latch-up. Thus, the N well-source structure of a semiconductor integrated circuit device including an SRAM with Full CMOS structure eliminates the need for providing a contact on the surfaces of the P.sup.+ -type diffusion region and the N.sup.+ -type diffusion region, to attain reduction in layout size.

    摘要翻译： 硅化钛（4）覆盖P +型扩散区（7）和N +型扩散区（8）的表面，以通过硅化钛（4）电连接扩散区（7,8），并且 硅化钛（4）被绝缘膜（10）覆盖。 因此，通过接触孔（3）和N +型扩散区（6），N阱（12）和N +型扩散区（8）向金属线（2）施加电源电位， 通过硅化钛（4）进一步提供用作PMOS晶体管的源极区的P +型扩散区（7）。 这消除了为防止闩锁而提供用于向扩散区域7和8提供电源电位以实现布局尺寸减小的任何接触的需要。 因此，包括具有全CMOS结构的SRAM的半导体集成电路器件的N阱源结构消除了在P +型扩散区域和N +型扩散区域的表面上提供接触的需要，以实现减少 布局尺寸。