公开(公告)号：US5539223A

公开(公告)日：1996-07-23

申请号：US36838

申请日：1993-03-25

申请人： Takeshi Sugoh ,  Hisashi Sugiyama

发明人： Takeshi Sugoh ,  Hisashi Sugiyama

IPC分类号： H01L21/82 ,  H01L21/822 ,  H01L23/528 ,  H01L27/04 ,  H01L27/118

CPC分类号： H01L27/11898 ,  H01L23/5286 ,  H01L24/06 ,  H01L2224/05554 ,  H01L2924/14

摘要： A semicustom integrated circuit comprises pads arranged on peripheral portions of a chip along the four sides thereof. Peripheral circuit cells are arranged on a part of the chip to the inside of the pads. An internal circuit is arranged on a part of the chip to the inside of the peripheral circuit cell. The peripheral circuit cells include an ECL level input circuit an ECL level output circuit, a TTL level input circuit and a TTL level output circuit. Main source lines are formed on the peripheral circuit cells so as to surround the internal circuit. The main source lines are connected to pads to which source potentials is applied. Branch source lines cross the main source lines and connected to a selected one of the peripheral circuit cells and said internal circuit. The main source lines are selectively connected to the branch source lines by an interlayer connecting source line.

摘要翻译： 半定制集成电路包括沿其四边布置在芯片的周边部分上的焊盘。 外围电路单元布置在芯片的一部分上至衬垫的内部。 内部电路布置在芯片的一部分到外围电路单元的内部。 外围电路单元包括ECL电平输入电路，ECL电平输出电路，TTL电平输入电路和TTL电平输出电路。 主源极线形成在外围电路单元上，以便围绕内部电路。 主源极线连接到施加源电位的焊盘。 分支源极线穿过主要源极线并连接到所选择的外围电路单元和所述内部电路中的一个。 主源极线通过层间连接源极线选择性地连接到分支源极线。

公开(公告)号：US5198704A

公开(公告)日：1993-03-30

申请号：US688511

申请日：1991-07-30

申请人： Yoshinori Nitta ,  Takeshi Sugoh ,  Hiroyuki Hara

发明人： Yoshinori Nitta ,  Takeshi Sugoh ,  Hiroyuki Hara

IPC分类号： H03K17/567 ,  H03K19/00 ,  H03K19/003 ,  H03K19/08 ,  H03K19/0944

CPC分类号： H03K19/09448 ,  H03K19/001 ,  H03K19/00353

摘要： In a Bi-CMOS output circuit constituted by combining a bipolar transistor and a CMOS circuit, in an output circuit obtained by connecting current paths of two bipolar transistors in series between a power source and ground, when the bipolar transistor connected to ground is driven by a bipolar transistor, an output current value can be assured when an output voltage is low. However, when the output voltage is high, a large current is supplied to the bipolar transistor to vary a power source voltage. Therefore, the output terminal of the MOS transistor is connected through a resistor to the grounded control signal input terminal of the bipolar transistor. Since the bipolar transistor connected to the ground is driven by a MOS transistor having drivability lower than that of a normal bipolar transistor, when the output voltage is low, a predetermined current can be assured. When the output voltage is high, supply of a large current can be prevented.

摘要翻译： PCT No.PCT / JP90 / 01277 Sec。 371日期1991年7月30日 102（e）日1991年7月30日PCT 1990年10月3日提交。在通过组合双极晶体管和CMOS电路构成的Bi-CMOS输出电路中，在通过将两个双极晶体管的电流路径 串联在电源和地之间，当连接到地的双极晶体管由双极晶体管驱动时，输出电压低时可以确保输出电流值。 然而，当输出电压高时，向双极晶体管提供大电流以改变电源电压。 因此，MOS晶体管的输出端子通过电阻器连接到双极晶体管的接地控制信号输入端。 由于连接到地的双极晶体管由具有低于正常双极晶体管的驱动能力的MOS晶体管驱动，所以当输出电压低时，可以确保预定的电流。 当输出电压高时，可以防止大电流的供给。

公开(公告)号：US5122683A

公开(公告)日：1992-06-16

申请号：US646207

申请日：1991-01-28

申请人： Takeshi Sugoh ,  Yasuhiro Sugimoto

发明人： Takeshi Sugoh ,  Yasuhiro Sugimoto

IPC分类号： H03K19/013 ,  H03K19/086

CPC分类号： H03K19/0136 ,  H03K19/086

摘要： An ECL circuit is designed such that at the beginning of the falling of the output level, the current flowing to an output terminal is rapidly led in the direction where it will be reduced, the potential of the output terminal at this time is directly detected, and a pull down transistor is controlled through a feedback loop, thus assuring high-speed operation and low power consumption. A control circuit is provided to regulate the collector current of the pull down transistor, which is used to drop the level of the potential at the output terminal. This control circuit is so designed that the base current of the pull down transistor is controlled by the operation of another, single transistor, and no capacitor which will obstruct the circuit integration is employed to drive the pull down transistor. The structure of this circuit is therefore advantageous in realizing higher integration.