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    Multiprocessor system, its control method, and information recording medium
    4.
    发明授权
    Multiprocessor system, its control method, and information recording medium 有权
    多处理器系统，其控制方法和信息记录介质

    公开(公告)号：US08266476B2

    公开(公告)日：2012-09-11

    申请号：US12444747

    申请日：2007-09-26

    申请人： Tsutomu Horikawa ,  Yasukichi Ohkawa

    发明人： Tsutomu Horikawa ,  Yasukichi Ohkawa

    IPC分类号： G06F11/00

    CPC分类号： G06F11/0793 ,  G06F11/0724

    摘要： To provide a multiprocessor system in which data transmission efficiency is unlikely to be affected if a damaged processor should exist among a plurality of processors. The multiprocessor system has a plurality of processing modules, including a predetermined number, being three or more, of processors, and a bus for relaying data transmission among the respective processing modules, and specifies at least one damaged processor; selects as a communication restricted processor subjected to communication restriction at least one of the processors connected to the bus at a position determined according to a position where the damaged processor is connected to the bus; and restricts data transmission by the communication restricted processor via the bus.

    摘要翻译： 为了提供一种多处理器系统，其中如果在多个处理器中存在损坏的处理器，则不太可能影响数据传输效率。 多处理器系统具有多个处理模块，包括三个或更多个处理器的预定数量，以及用于在各个处理模块之间中继数据传输的总线，并指定至少一个损坏的处理器; 选择经受通信限制的通信限制处理器，所述通信限制处理器在根据所述损坏的处理器连接到所述总线的位置确定的位置处连接到所述总线的所述处理器中的至少一个处理器; 并通过总线限制通信限制处理器的数据传输。

    Information Processing Method, Information Processing Apparatus, And Server
    5.
    发明申请
    Information Processing Method, Information Processing Apparatus, And Server 有权
    信息处理方法，信息处理装置和服务器

    公开(公告)号：US20080163228A1

    公开(公告)日：2008-07-03

    申请号：US11909196

    申请日：2006-04-06

    申请人： Kenichi Murata ,  Tsutomu Horikawa

    发明人： Kenichi Murata ,  Tsutomu Horikawa

    IPC分类号： G06F9/46

    CPC分类号： G06F9/505

    摘要： An information processing method includes: accepting a request for execution of a new task; identifying at least either one of a processing time required for the new task and a bus bandwidth required for processing the new task; making at least either one of comparisons between a total required processing time, which is a sum of processing times required for the new task and a reserved task reserved on a scheduler for indicating a procedure pertaining to a plurality of tasks, and a processing time available in an apparatus that executes those tasks, and between a total required bus bandwidth, which is a sum of bus bandwidths required for processing the reserved task and the new task, and a bus bandwidth available in the apparatus that executes those tasks; determining whether the new task is executable or not, based on the result of comparison(s); making a reservation for the new task on the scheduler if the new task is determined to be executable; and processing the tasks including the new task which is determined to be executable based on the scheduler, wherein the determining of whether the new task is executable or not includes acquiring priority information on the new task, and whether the new task is executable or not is determined based on the priority information acquired.

    摘要翻译： 一种信息处理方法，包括：接受执行新任务的请求; 识别新任务所需的处理时间和处理新任务所需的总线带宽中的至少一个; 进行总需要的处理时间之间的比较中的至少一个，其是新任务所需的处理时间和在调度器上保留的用于指示与多个任务相关的过程的保留任务的总和以及可用的处理时间 在执行这些任务的装置中，以及在总需要总线带宽之间以及在执行这些任务的装置中可用的总线带宽，其是处理保留任务所需的总线带宽和新任务之和; 基于比较的结果确定新任务是否可执行; 如果新任务被确定为可执行，则对调度器上的新任务进行预留; 并且基于所述调度器处理包括被确定为可执行的新任务的任务，其中所述确定所述新任务是否可执行包括获取关于所述新任务的优先级信息，以及所述新任务是否可执行 根据所获得的优先级信息确定。

    Information processing apparatus and access control method capable of high-speed data access
    6.
    发明授权
    Information processing apparatus and access control method capable of high-speed data access 有权
    能够进行高速数据访问的信息处理装置和访问控制方法

    公开(公告)号：US08060679B2

    公开(公告)日：2011-11-15

    申请号：US11760853

    申请日：2007-06-11

    申请人： Masaaki Nozaki ,  Tsutomu Horikawa ,  Kenichi Murata

    发明人： Masaaki Nozaki ,  Tsutomu Horikawa ,  Kenichi Murata

    IPC分类号： G06F12/00

    CPC分类号： G06F13/1642 ,  G06F13/364

    摘要： Requestors acquire tokens before issuing access requests to a memory controller. The access requests issued are accumulated in a command queue of the memory controller. When the amount of access requests accumulated in the command queue is smaller than or equal to a first threshold, or in level 0, tokens are generated at a rate equivalent to 200% of a bus bandwidth. If the amount of accumulation is greater than the first threshold and is smaller than or equal to a second threshold, i.e., in level 1, tokens are generated at a rate equivalent to the bus bandwidth. If the amount of accumulation exceeds the second threshold, the token generation is stopped.

    摘要翻译： 请求者在向存储器控制器发出访问请求之前获取令牌。 发出的访问请求被存储在存储器控制器的命令队列中。 当在命令队列中累积的访问请求量小于或等于第一阈值时，或者在级别0中，以相当于总线带宽的200％的速率生成令牌。 如果累积量大于第一阈值并且小于或等于第二阈值，即在级别1中，则以与总线带宽相当的速率生成令牌。 如果累积量超过第二阈值，则令牌生成被停止。

    MULTIPROCESSOR SYSTEM, ITS CONTROL METHOD, AND INFORMATION RECORDING MEDIUM
    7.
    发明申请
    MULTIPROCESSOR SYSTEM, ITS CONTROL METHOD, AND INFORMATION RECORDING MEDIUM 有权
    多处理器系统，其控制方法和信息记录介质

    公开(公告)号：US20100023665A1

    公开(公告)日：2010-01-28

    申请号：US12444747

    申请日：2007-09-26

    申请人： Tsutomu Horikawa ,  Yasukichi Ohkawa

    发明人： Tsutomu Horikawa ,  Yasukichi Ohkawa

    IPC分类号： G06F13/362

    CPC分类号： G06F11/0793 ,  G06F11/0724

    摘要： To provide a multiprocessor system in which data transmission efficiency is unlikely to be affected if a damaged processor should exist among a plurality of processors. The multiprocessor system has a plurality of processing modules, including a predetermined number, being three or more, of processors, and a bus for relaying data transmission among the respective processing modules, and specifies at least one damaged processor; selects as a communication restricted processor subjected to communication restriction at least one of the processors connected to the bus at a position determined according to a position where the damaged processor is connected to the bus; and restricts data transmission by the communication restricted processor via the bus.

    摘要翻译： 为了提供一种多处理器系统，其中如果在多个处理器中存在损坏的处理器，则不太可能影响数据传输效率。 多处理器系统具有多个处理模块，包括三个或更多个处理器的预定数量，以及用于在各个处理模块之间中继数据传输的总线，并指定至少一个损坏的处理器; 选择经受通信限制的通信限制处理器，所述通信限制处理器在根据所述损坏的处理器连接到所述总线的位置确定的位置处连接到所述总线的所述处理器中的至少一个处理器; 并通过总线限制通信限制处理器的数据传输。

    Methods and apparatus for controlling access to resources in an information processing system
    8.
    发明授权
    Methods and apparatus for controlling access to resources in an information processing system 有权
    控制信息处理系统中资源访问的方法和装置

    公开(公告)号：US07617344B2

    公开(公告)日：2009-11-10

    申请号：US11760858

    申请日：2007-06-11

    申请人： Masaaki Nozaki ,  Tsutomu Horikawa

    发明人： Masaaki Nozaki ,  Tsutomu Horikawa

    IPC分类号： G06F13/14

    CPC分类号： G06F13/1642

    摘要： Requestors issue access requests to a memory controller. The access requests issued are accumulated in a command queue of the memory controller. When the amount of access requests accumulated in the command queue is smaller than or equal to a threshold, a free pass (FP) is granted to specified requesters. When issuing access requests, requesters request and acquire tokens before issuing the access requests if they have no FP granted. If the requesters have an FP, they simply issue the access requests.

    摘要翻译： 请求者向存储控制器发出访问请求。 发出的访问请求被存储在存储器控制器的命令队列中。 当在命令队列中累积的访问请求量小于或等于阈值时，向指定的请求者授予自由通过（FP）。 发出访问请求时，如果发放访问请求没有FP，则请求者在发出访问请求之前请求并获取令牌。 如果请求者有FP，他们只需发出访问请求。

    Kernel creator for creating kernel capable of executing entertainment processing using a peripheral device
    9.
    发明授权
    Kernel creator for creating kernel capable of executing entertainment processing using a peripheral device 有权
    用于创建能够使用外围设备执行娱乐处理的内核的内核创建者

    公开(公告)号：US06754724B2

    公开(公告)日：2004-06-22

    申请号：US09797515

    申请日：2001-03-01

    申请人： Tsutomu Horikawa ,  Tadayasu Hakamatani

    发明人： Tsutomu Horikawa ,  Tadayasu Hakamatani

    IPC分类号： G06F300

    CPC分类号： G06F9/547 ,  G06F13/126 ,  G06F13/28

    摘要： An entertainment apparatus includes a storage unit that stores outside a kernel a device driver for a peripheral device. To make the peripheral device operable, a CPU causes an I/O processor to execute the device driver using a remote procedure call. Data is transferred between the peripheral device and the CPU through a direct memory access using a communication protocol that is commonly used in the apparatus.

    摘要翻译： 娱乐装置包括：存储部，其在外部存储有用于外围设备的设备驱动器。 为了使外围设备可操作，CPU使I / O处理器使用远程过程调用来执行设备驱动程序。 数据通过使用通常在设备中使用的通信协议的直接存储器访问在外围设备和CPU之间传送。

    Information processing method, information processing apparatus, and server
    10.
    发明授权
    Information processing method, information processing apparatus, and server 有权
    信息处理方法，信息处理装置和服务器

    公开(公告)号：US08266621B2

    公开(公告)日：2012-09-11

    申请号：US11909196

    申请日：2006-04-06

    申请人： Kenichi Murata ,  Tsutomu Horikawa

    发明人： Kenichi Murata ,  Tsutomu Horikawa

    IPC分类号： G06F9/46

    CPC分类号： G06F9/505

    摘要： In an information processing system, when a request for execution of a new task is accepted, one or more of the required processing time and bus bandwidth for the new task are identified. A total required processing time, which is a sum of processing times required for the new task and a task reserved on a scheduler for indicating a procedure pertaining to a plurality of tasks, is compared with a processing time available in an apparatus executing those tasks. Similarly, a total required bus bandwidth, which is a sum of bus bandwidths required for processing the reserved task and the new task, is compared with a bus bandwidth available in the apparatus. Based on the result of the comparisons, it is determined whether the new task is executable.

    摘要翻译： 在信息处理系统中，当接受执行新任务的请求时，识别新任务所需的处理时间和总线带宽中的一个或多个。 与执行这些任务的装置中可用的处理时间相比，将所需的处理时间（其为新任务所需的处理时间和在调度器上保留的用于指示与多个任务相关的过程）的处理时间的总和进行比较。 类似地，将总需求总线带宽（其是处理保留任务所需的总线带宽和新任务的总和）与设备中可用的总线带宽进行比较。 基于比较的结果，确定新任务是否可执行。