公开(公告)号：US5774470A

公开(公告)日：1998-06-30

申请号：US524040

申请日：1995-09-06

申请人： Takushi Nishiya ,  Shoichi Miyazawa ,  Kazutoshi Ashikawa ,  Ryushi Shimokawa ,  Seiichi Mita

发明人： Takushi Nishiya ,  Shoichi Miyazawa ,  Kazutoshi Ashikawa ,  Ryushi Shimokawa ,  Seiichi Mita

IPC分类号： G06F11/10 ,  G11B20/10 ,  G11B20/18 ,  H03H15/00 ,  H03H17/00 ,  H03H21/00 ,  H03M13/23 ,  H03M13/41 ,  H04B3/04

CPC分类号： G11B20/10055 ,  G11B20/10009 ,  G11B20/18 ,  H03M13/41 ,  H03M13/6331 ,  H03M13/6505

摘要： A playback signal processing circuit for reducing decode errors and enabling high-density digital magnetic recording and a digital magnetic recording reproducing unit using the playback signal processing circuit are provided. An estimated waveform generation circuit uses the decoding result of a PRML channel to generate an ideal playback signal waveform. A subtractor provides a waveform representing a difference between the waveform and an actual playback signal. There is a high probability that error bits will occur at an interval of two or four bits because of the nature of GCR code and maximum-likelihood decoding; in the error state of each bit, one bit is incremented by one with respect to the correct bit value and the other signal bit is decremented by one. From this fact, an error detection circuit discriminates an error difference waveform pattern and an error discrimination circuit detects an error bit interval, whereby an error correction circuit carries out error bit correction.

摘要翻译： 提供了一种用于减少解码错误并实现高密度数字磁记录的重放信号处理电路和使用重放信号处理电路的数字磁记录再现单元。 估计波形生成电路使用PRML通道的解码结果来产生理想的重放信号波形。 减法器提供表示波形和实际重放信号之间的差异的波形。 由于GCR码的性质和最大似然解码，错误位将以两位或四位的间隔发生的概率很高; 在每个位的错误状态下，一个比特相对于正确的比特值递增1，另一个比特递减1。 根据该事实，误差检测电路鉴别误差波形图案，误差鉴别电路检测误差位间隔，由此误差校正电路进行错误位校正。

公开(公告)号：US06661594B2

公开(公告)日：2003-12-09

申请号：US10277695

申请日：2002-10-23

申请人： Naoki Satoh ,  Seiichi Mita ,  Shoichi Miyazawa ,  Terumi Takashi ,  Yosuke Hori ,  Yoshiju Watanabe ,  Akihiko Hirano ,  Satoshi Minoshima ,  Hideki Miyasaka ,  Toshihiro Nitta ,  Tomoaki Hirai ,  Ryushi Shimokawa ,  Koji Shida ,  Yasuhide Ouchi

发明人： Naoki Satoh ,  Seiichi Mita ,  Shoichi Miyazawa ,  Terumi Takashi ,  Yosuke Hori ,  Yoshiju Watanabe ,  Akihiko Hirano ,  Satoshi Minoshima ,  Hideki Miyasaka ,  Toshihiro Nitta ,  Tomoaki Hirai ,  Ryushi Shimokawa ,  Koji Shida ,  Yasuhide Ouchi

IPC分类号： G11B535

CPC分类号： G11B20/10055 ,  G11B5/035 ,  G11B5/09 ,  G11B20/10009 ,  G11B20/10481

摘要： A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.

摘要翻译： 一种用于至少包括AGC，PLL，LPF，均衡器电路和检测电路的磁记录/再现装置的信号处理电路，其中通过定义均衡器电路的结构形成系数补偿电路，错误 提供检测电路，其通过接收来自检测电路的输入而工作，并且LSI由多个模拟和数字芯片形成，并且模拟和数字芯片通过电流输出型D / A转换器连接至少至少 AGC和PLL。

公开(公告)号：US5818655A

公开(公告)日：1998-10-06

申请号：US506635

申请日：1995-07-25

申请人： Naoki Satoh ,  Seiichi Mita ,  Shoichi Miyazawa ,  Terumi Takashi ,  Yosuke Hori ,  Yoshiju Watanabe ,  Akihiko Hirano ,  Satoshi Minoshima ,  Hideki Miyasaka ,  Toshihiro Nitta ,  Tomoaki Hirai ,  Ryushi Shimokawa ,  Koji Shida ,  Yasuhide Ouchi

发明人： Naoki Satoh ,  Seiichi Mita ,  Shoichi Miyazawa ,  Terumi Takashi ,  Yosuke Hori ,  Yoshiju Watanabe ,  Akihiko Hirano ,  Satoshi Minoshima ,  Hideki Miyasaka ,  Toshihiro Nitta ,  Tomoaki Hirai ,  Ryushi Shimokawa ,  Koji Shida ,  Yasuhide Ouchi

IPC分类号： G11B5/035 ,  G11B5/09 ,  G11B20/10

CPC分类号： G11B20/10055 ,  G11B20/10009 ,  G11B20/10481 ,  G11B5/035 ,  G11B5/09

摘要： A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.

公开(公告)号：US06452736B1

公开(公告)日：2002-09-17

申请号：US08450245

申请日：1995-05-25

申请人： Eisaku Saiki ,  Shintaro Suzumura ,  Terumi Takashi ,  Kazutoshi Ashikawa ,  Tsuguyoshi Hirooka ,  Shoichi Miyazawa ,  Masashi Mori

发明人： Eisaku Saiki ,  Shintaro Suzumura ,  Terumi Takashi ,  Kazutoshi Ashikawa ,  Tsuguyoshi Hirooka ,  Shoichi Miyazawa ,  Masashi Mori

IPC分类号： G11B509

CPC分类号： G11B5/09 ,  G11B5/012 ,  G11B5/02 ,  G11B20/10009 ,  H03F3/45089 ,  H03F3/45103 ,  H03F3/72 ,  H03F2203/45316

摘要： A magnetic recording and reproducing apparatus includes a read/write signal processor having a write data generator arranged to be of an interleave system and transmitting/receiving data to/from the read/write amplifier via a plurality of signal lines. In addition, the read/write amplifier has a compound circuit provided for the write data of the interleave system from the read/write signal processor and is formed as an integrated circuit, moreover, a 1/2 prescaler is provided at the output of the write data generator, transmitting and receiving write data in Non-Return-To-Zero-Interleave CODE.

摘要翻译： 磁记录和再现装置包括一个读/写信号处理器，该读/写信号处理器具有布置成交错系统的写数据发生器，并经由多个信号线向读/写放大器发送/接收数据。 此外，读/写放大器具有为来自读/写信号处理器的交错系统的写入数据提供的复合电路，并且形成为集成电路，此外，在该输出处提供1/2预分频器 写数据生成器，在非归零交错CODE中发送和接收写入数据。

公开(公告)号：US06700721B2

公开(公告)日：2004-03-02

申请号：US10191562

申请日：2002-07-10

申请人： Eisaku Saiki ,  Shintaro Suzumura ,  Terumi Takashi ,  Kazutoshi Ashikawa ,  Tsuguyoshi Hirooka ,  Shoichi Miyazawa ,  Masashi Mori

发明人： Eisaku Saiki ,  Shintaro Suzumura ,  Terumi Takashi ,  Kazutoshi Ashikawa ,  Tsuguyoshi Hirooka ,  Shoichi Miyazawa ,  Masashi Mori

IPC分类号： G11B509

CPC分类号： G11B5/09 ,  G11B5/012 ,  G11B5/02 ,  G11B20/10009 ,  H03F3/45089 ,  H03F3/45103 ,  H03F3/72 ,  H03F2203/45316

摘要： A magnetic recording and reproducing apparatus includes a R/W signal processor having a write data generator arranged to be of an interleave system and transmitting/receiving data to/from the R/W amplifier via a plurality of signal lines. In addition, the R/W amplifier has a compound circuit provided for the write data of the interleave system from the R/W signal processor and is formed as an integrated circuit, moreover, a ½ prescaler is provided at the output of the write data generator, making transmitting and receiving write data in NRZI CODE.

摘要翻译： 磁记录和重放装置包括一个R / W信号处理器，其具有被布置成交错系统的写入数据发生器，并经由多个信号线向/从R / W放大器发送/接收数据。 此外，R / W放大器具有为来自R / W信号处理器的交错系统的写入数据提供的复合电路，并且形成为集成电路，此外，在写入数据的输出端提供½预分频器 发送器，在NRZI CODE中发送和接收写入数据。

公开(公告)号：US5872666A

公开(公告)日：1999-02-16

申请号：US560387

申请日：1995-11-17

申请人： Eisaku Saiki ,  Kazutosi Ashikawa ,  Seiichi Mita ,  Shintaro Suzumura ,  Shoichi Miyazawa ,  Tsuguyoshi Hirooka

发明人： Eisaku Saiki ,  Kazutosi Ashikawa ,  Seiichi Mita ,  Shintaro Suzumura ,  Shoichi Miyazawa ,  Tsuguyoshi Hirooka

IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  H03H15/00 ,  H03H17/00 ,  H03H21/00 ,  H03M13/23 ,  H04B3/04 ,  H04L25/497

CPC分类号： G11B20/10055 ,  G11B20/10009 ,  G11B5/012 ,  G11B5/09

摘要： Reproducing apparatus with an A/D (analog-to-digital) converter, which realizes high-accuracy data sampling, high-speed data transfer, low dissipation power and low cost. PR (partial response) processing is performed by receiving encoded signals, delaying the received signals on the basis of a reference clock, and adding the delayed signals and the received signals in analog signal form. The added signals are converted into digital values on the basis of the reference clock by the A/D converter, and Viterbi decoding is performed on the basis of the converted digital values. Owing to the PR processing which is performed at a stage preceding the A/D converter, a frequency band for the A/D conversion can be lowered, and hence, the high-accuracy data sampling is permitted.

摘要翻译： 具有A / D（模拟 - 数字）转换器的再现装置实现了高精度数据采样，高速数据传输，低功耗和低成本。 PR（部分响应）处理通过接收编码信号，基于参考时钟延迟接收信号，并将延迟信号和接收信号相加在模拟信号形式中来执行。 所附加的信号由A / D转换器基于参考时钟转换为数字值，并且基于转换的数字值执行维特比解码。 由于在A / D转换器之前的阶段执行的PR处理可以降低A / D转换的频带，因此允许高精度数据采样。

公开(公告)号：US20060285238A1

公开(公告)日：2006-12-21

申请号：US11507436

申请日：2006-08-22

申请人： Motoyasu Tsunoda ,  Shoichi Miyazawa ,  Yukie Miyazawa ,  Hitoshi Ogawa ,  Ryutaro Horita ,  Takashi Nara ,  Masatoshi Nishina ,  Katsumi Yamamoto

发明人： Motoyasu Tsunoda ,  Shoichi Miyazawa ,  Yukie Miyazawa ,  Hitoshi Ogawa ,  Ryutaro Horita ,  Takashi Nara ,  Masatoshi Nishina ,  Katsumi Yamamoto

IPC分类号： G11B5/09 ,  G11B5/596

CPC分类号： G11B20/1217 ,  G11B5/59605 ,  G11B20/24 ,  G11B21/106 ,  G11B2020/1287 ,  G11B2020/1298

摘要： A signal processing device having a feature of analog-to-digital converting a burst signal has a feature of selecting data bus to notify a disk control device 2 of a conversion result via an NRZ data bus. The disk control device 2 includes means for storing the result of the analog-to-digital conversion of said servo positional signal. The positional signal of a head of the disk device is digitalized in an R/W channel. Sampling for digital conversion is performed in only a window which is defined only in the vicinity of peaks of the positional signal. The values of peaks which are obtained by sampling are averaged by an averaging circuit. This enables the influence of noise occurred outside of the window to be eliminated. Although the noise in the window is sampled, its adverse influence is suppressed by the averaging processing.

公开(公告)号：US5953513A

公开(公告)日：1999-09-14

申请号：US506002

申请日：1995-07-24

申请人： Eisaku Saiki ,  Takashi Oeda ,  Shoichi Miyazawa ,  Kazuo Shigematsu ,  Yasunori Kaneda

发明人： Eisaku Saiki ,  Takashi Oeda ,  Shoichi Miyazawa ,  Kazuo Shigematsu ,  Yasunori Kaneda

IPC分类号： G06F13/00

CPC分类号： G06F13/00

摘要： The recording and reproducing apparatus comprises an Small Computer System Interface (SCSI) controller, an optical disc device, a magnetic disc device, a disc controller which controls the optical disc device and the magnetic disc device, connectors which connects directly the optical disc device and the magnetic disc device, and a selector which selects one of the optical disc device and the magnetic disc device. A Copy or Verify command is carried out within the apparatus without an SCSI bus, and data are transferred through the connector. Therefore occupation of the SCSI bus and overhead of the SCSI protocol are eliminated, and the apparatus is miniaturized by common use of the SCSI controller and the disc controller.

摘要翻译： 记录和再现装置包括小型计算机系统接口（SCSI）控制器，光盘装置，磁盘装置，控制光盘装置和磁盘装置的盘控制器，直接连接光盘装置的连接器和 磁盘装置和选择光盘装置和磁盘装置之一的选择器。 在没有SCSI总线的设备内执行复制或验证命令，数据通过连接器传输。 因此，SCSI总线的占用和SCSI协议的开销被消除，并且该装置通过SCSI控制器和盘控制器的常见使用而小型化。

公开(公告)号：US5479619A

公开(公告)日：1995-12-26

申请号：US279051

申请日：1994-07-22

申请人： Yukari Nagashige ,  Shoichi Miyazawa ,  Kunio Watanabe ,  Kouji Shida ,  Shinichi Kojima

发明人： Yukari Nagashige ,  Shoichi Miyazawa ,  Kunio Watanabe ,  Kouji Shida ,  Shinichi Kojima

IPC分类号： G06F1/32 ,  G06F13/10 ,  G06F15/78 ,  G06F13/00

CPC分类号： G06F1/3215 ,  G06F1/325 ,  G06F1/3268 ,  Y02B60/1246 ,  Y02B60/32

摘要： A peripheral equipment control LSI interposed between an SCSI bus connected to a main CPU and peripheral equipment such as a file device. The LSI is divided into two major blocks. One block recognizes an SCSI protocol ID signal sent over the SCSI bus. The other block generates a signal that causes the other block to leave a sleep state (low power dissipation mode). In a sate in which a command is awaited from the main CPU, the peripheral equipment control LSI allows the block containing the ID recognition part to remain active while the other block is kept in the sleep state. On receiving an ID-based selected (access) signal from the main CPU, the LSI detects the start of an access operation and causes the other block to leave its sleep state and to become active.

摘要翻译： 插入在连接到主CPU的SCSI总线和诸如文件装置的外围设备之间的外围设备控制LSI。 LSI分为两大块。 一个块识别通过SCSI总线发送的SCSI协议ID信号。 另一个块产生一个信号，导致另一个块离开睡眠状态（低功耗模式）。 在从主CPU等待命令的状态下，外围设备控制LSI允许包含ID识别部分的块保持活动，而另一个块保持在睡眠状态。 在从主CPU接收到基于ID的选择（访问）信号时，LSI检测到访问操作的开始，并使其他块离开其休眠状态并变为活动状态。

公开(公告)号：US06445522B1

公开(公告)日：2002-09-03

申请号：US09716326

申请日：2000-11-21

申请人： Motoyasu Tsunoda ,  Shoichi Miyazawa ,  Hitoshi Ogawa ,  Ryutaro Horita ,  Takashi Nara ,  Masatoshi Nishina ,  Katsumi Yamamoto

发明人： Motoyasu Tsunoda ,  Shoichi Miyazawa ,  Hitoshi Ogawa ,  Ryutaro Horita ,  Takashi Nara ,  Masatoshi Nishina ,  Katsumi Yamamoto

IPC分类号： G11B509

CPC分类号： G11B20/1217 ,  G11B5/59605 ,  G11B20/24 ,  G11B21/106 ,  G11B2020/1287 ,  G11B2020/1298

摘要： A signal processing device for analog-to-digital converting a burst signal has a feature of selecting a data bus to notify a disk control device of a conversion result via an NRZ data bus. The disk control device stores the result of the analog-to-digital conversion of the servo positional signal. The positional signal of a head of the disk device is digitalized in a R/W channel. Sampling for digital conversion is performed in only a window which is defined only in the vicinity of peaks of the positional signal. The values of peaks which are obtained by sampling are averaged by an averaging circuit. This enables the influence of noise occurred outside of the window to be eliminated. Although the noise in the window is sampled, its adverse influence is suppressed by the averaging processing.

摘要翻译： 用于模数转换突发信号的信号处理装置具有通过NRZ数据总线选择数据总线以向盘控制装置通知转换结果的特征。 磁盘控制装置存储伺服位置信号的模数转换的结果。 磁盘设备的磁头的位置信号在R / W通道中被数字化。 仅在仅在位置信号的峰值附近定义的窗口中执行用于数字转换的采样。 通过采样获得的峰值由平均电路进行平均。 这使得可以消除在窗外发生的噪声的影响。 虽然窗口中的噪声被采样，但其不利影响被平均处理抑制。