公开(公告)号：US06373407B1

公开(公告)日：2002-04-16

申请号：US09255733

申请日：1999-02-23

申请人： Takushi Nishiya ,  Tatsuya Hirai ,  Seiichi Mita ,  Takashi Nara ,  Yoichi Uehara ,  Hiroshi Ide ,  Kyoko Tsukano ,  Yoshiju Watanabe

发明人： Takushi Nishiya ,  Tatsuya Hirai ,  Seiichi Mita ,  Takashi Nara ,  Yoichi Uehara ,  Hiroshi Ide ,  Kyoko Tsukano ,  Yoshiju Watanabe

IPC分类号： H03M700

CPC分类号： H03M5/145 ,  G11B20/1426 ,  G11B2020/1446

摘要： The computer system includes a host system, a recording medium, and a digital signal decoder connected to the host system and the recording medium. The digital signal decoder receives M-bit data and generates an N-bit code word from the M-bit data. The number of consecutive bits of 1 in the code word is not larger than a first predetermined number K, and the number of consecutive bits of 0 is not larger than a second predetermined number L. When data is recorded/reproduced by a method such as NRZI (Non-Return to Zero Inverted), or the like, there is a defect in that the number of transitions of data is larger in a code with a high data encoding rate, and the run length of zero is long thereby increasing the data decoding error rate with the recording/reproducing of data. In the digital signal decoder according to the present invention, any code word includes at most 3 consecutive bits of 1, and at most 11 consecutive bits of 0, so that the data decoding error rate can be reduced.

摘要翻译： 计算机系统包括主机系统，记录介质和连接到主机系统和记录介质的数字信号解码器。 数字信号解码器接收M位数据并从M位数据生成N位代码字。 代码字中的连续比特数1不大于第一预定数K，连续比特数0不大于第二预定数L.当通过诸如以下方法记录/再现数据时 NRZI（不归零归零）等，存在数据的转换次数较大的缺点，数据编码速率高的代码，零的行程长，从而增加数据 解码错误率与数据的记录/再现。 在根据本发明的数字信号解码器中，任何代码字包括最多3个连续位1和至多11个连续位0，从而可以减少数据解码错误率。

公开(公告)号：US5774470A

公开(公告)日：1998-06-30

申请号：US524040

申请日：1995-09-06

申请人： Takushi Nishiya ,  Shoichi Miyazawa ,  Kazutoshi Ashikawa ,  Ryushi Shimokawa ,  Seiichi Mita

发明人： Takushi Nishiya ,  Shoichi Miyazawa ,  Kazutoshi Ashikawa ,  Ryushi Shimokawa ,  Seiichi Mita

IPC分类号： G06F11/10 ,  G11B20/10 ,  G11B20/18 ,  H03H15/00 ,  H03H17/00 ,  H03H21/00 ,  H03M13/23 ,  H03M13/41 ,  H04B3/04

CPC分类号： G11B20/10055 ,  G11B20/10009 ,  G11B20/18 ,  H03M13/41 ,  H03M13/6331 ,  H03M13/6505

摘要： A playback signal processing circuit for reducing decode errors and enabling high-density digital magnetic recording and a digital magnetic recording reproducing unit using the playback signal processing circuit are provided. An estimated waveform generation circuit uses the decoding result of a PRML channel to generate an ideal playback signal waveform. A subtractor provides a waveform representing a difference between the waveform and an actual playback signal. There is a high probability that error bits will occur at an interval of two or four bits because of the nature of GCR code and maximum-likelihood decoding; in the error state of each bit, one bit is incremented by one with respect to the correct bit value and the other signal bit is decremented by one. From this fact, an error detection circuit discriminates an error difference waveform pattern and an error discrimination circuit detects an error bit interval, whereby an error correction circuit carries out error bit correction.

摘要翻译： 提供了一种用于减少解码错误并实现高密度数字磁记录的重放信号处理电路和使用重放信号处理电路的数字磁记录再现单元。 估计波形生成电路使用PRML通道的解码结果来产生理想的重放信号波形。 减法器提供表示波形和实际重放信号之间的差异的波形。 由于GCR码的性质和最大似然解码，错误位将以两位或四位的间隔发生的概率很高; 在每个位的错误状态下，一个比特相对于正确的比特值递增1，另一个比特递减1。 根据该事实，误差检测电路鉴别误差波形图案，误差鉴别电路检测误差位间隔，由此误差校正电路进行错误位校正。

公开(公告)号：US06980385B2

公开(公告)日：2005-12-27

申请号：US10914243

申请日：2004-08-10

申请人： Takatoshi Kato ,  Takushi Nishiya ,  Hideyuki Yamakawa ,  Takashi Nara ,  Nobuaki Nakai ,  Hiroshi Ide ,  Shintaro Suzumura ,  Terumi Takashi

发明人： Takatoshi Kato ,  Takushi Nishiya ,  Hideyuki Yamakawa ,  Takashi Nara ,  Nobuaki Nakai ,  Hiroshi Ide ,  Shintaro Suzumura ,  Terumi Takashi

IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/14

CPC分类号： G11B20/10009 ,  G11B5/012 ,  G11B5/09 ,  G11B20/1403

摘要： In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.

摘要翻译： 为了产生具有更高精度的采样时钟，同步信号发生电路设置有相位误差检测器，检测基于FDTS算法数字化的读出信号的相位误差和控制振荡频率的VCO 基于由相位误差检测器检测到的相位误差，由VCO产生同步信号。 基于由同步信号发生电路产生的同步信号，ADC对读出的信号进行数字化。 然后，数字化读出信号由检测电路转换成二进制数据。

公开(公告)号：US06791776B2

公开(公告)日：2004-09-14

申请号：US09793924

申请日：2001-02-28

申请人： Takatoshi Kato ,  Takushi Nishiya ,  Hideyuki Yamakawa ,  Takashi Nara ,  Nobuaki Nakai ,  Hiroshi Ide ,  Shintaro Suzumura ,  Terumi Takashi

发明人： Takatoshi Kato ,  Takushi Nishiya ,  Hideyuki Yamakawa ,  Takashi Nara ,  Nobuaki Nakai ,  Hiroshi Ide ,  Shintaro Suzumura ,  Terumi Takashi

IPC分类号： G11B509

CPC分类号： G11B20/10009 ,  G11B5/012 ,  G11B5/09 ,  G11B20/1403

摘要： In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.

摘要翻译： 为了产生具有更高精度的采样时钟，同步信号发生电路设置有相位误差检测器，检测基于FDTS算法数字化的读出信号的相位误差和控制振荡频率的VCO 基于由相位误差检测器检测到的相位误差，由VCO产生同步信号。 基于由同步信号发生电路产生的同步信号，ADC对读出的信号进行数字化。 然后，数字化读出信号由检测电路转换成二进制数据。

公开(公告)号：US06326838B1

公开(公告)日：2001-12-04

申请号：US09389582

申请日：1999-09-03

申请人： Hiroshi Kimura ,  Takushi Nishiya ,  Takatoshi Kato ,  Takashi Nara ,  Seiichi Mita

发明人： Hiroshi Kimura ,  Takushi Nishiya ,  Takatoshi Kato ,  Takashi Nara ,  Seiichi Mita

IPC分类号： H03B100

CPC分类号： H03H11/0422

摘要： A transconductance control circuit is composed of a replica transconductance amplifier and resistance, a reference voltage source, first selectors, a differential amplifier, a voltage-current translate circuit with characteristics equal to the transconductance amplifier which constitutes analog filters. A first switch of the first selectors is connectable for the reference voltage source, and every constant period is made to connect it using clocks at the reference voltage source. A second switch of second selectors is connectable for plural capacitors, and every constant period is made to connect it using clocks at the capacitors.

摘要翻译： 跨导控制电路由复制跨导放大器和电阻，参考电压源，第一选择器，差分放大器，具有等于构成模拟滤波器的跨导放大器的特性的电压 - 电流平移电路组成。 第一选择器的第一开关可连接到参考电压源，并且每个恒定周期都使用参考电压源的时钟进行连接。 第二选择器的第二开关可连接多个电容器，并且每个恒定周期都使用电容器上的时钟来连接。

公开(公告)号：US5175797A

公开(公告)日：1992-12-29

申请号：US575951

申请日：1990-08-31

申请人： Motohisa Funabashi ,  Takushi Nishiya ,  Masahiro Oba ,  Mikio Yoda ,  Kazuo Kera ,  Kiyomi Mori

发明人： Motohisa Funabashi ,  Takushi Nishiya ,  Masahiro Oba ,  Mikio Yoda ,  Kazuo Kera ,  Kiyomi Mori

IPC分类号： G06F15/18 ,  G06F9/44 ,  G06F19/00 ,  G06N3/00 ,  G06N3/04 ,  G06N5/04 ,  G06N7/02 ,  G06N99/00

CPC分类号： G06N3/0436 ,  Y10S706/90

摘要： A method and apparatus of a learning type decision support system are provided for improved acquisition of a priori knowledge from the system object and expression of non-linear structures in the object. The system is comprised of a learning module and an executing module for outputting advice and process manipulate command values to system users by receiving input data comprising on-line data and file data. The learning module comprises (1) a symbolized dictionary unit for generating a symbolized dictionary for giving a symbolic name in accordance with a pattern comprised of a combination of the values of the input data by giving examples of a pair of the pattern and the symbolic name; (2) a preprocessing unit for transforming at least a portion of the input data into the symbolic name with reference to the symbolic dictionary generated; and, (3) a model generating unit for determining an unknown parameter contained in a predetermined skeleton model to transform the preprocessed results into desired advice and manipulation command values. The executing module arithmetically processes the input data to output the advice and the manipulation command values by using the symbolized dictionary generated by the learning module and the generated model.

摘要翻译： 提供了一种学习型决策支持系统的方法和装置，用于从系统对象中改进对先验知识的获取和对象中非线性结构的表达。 该系统包括学习模块和执行模块，用于通过接收包括在线数据和文件数据的输入数据来向系统用户输出建议和处理操作命令值。 学习模块包括：（1）符号字典单元，用于通过给出一对图案和符号名称的示例来生成符号字典，用于根据包括输入数据的值的组合的图案来给出符号名称 ; （2）预处理单元，用于参照所生成的符号字典将输入数据的至少一部分变换为符号名称; （3）模型生成单元，用于确定包含在预定骨架模型中的未知参数，以将预处理结果转换为期望的建议和操作命令值。 执行模块通过使用由学习模块和生成的模型生成的符号化字典来对输入数据进行算术处理以输出建议和操作命令值。

公开(公告)号：US5109431A

公开(公告)日：1992-04-28

申请号：US526000

申请日：1990-05-21

申请人： Takushi Nishiya ,  Motohisa Funabashi ,  Kazuo Kera

发明人： Takushi Nishiya ,  Motohisa Funabashi ,  Kazuo Kera

IPC分类号： G06K9/48 ,  G06K9/68 ,  G06T7/20 ,  G06T9/00

CPC分类号： G06K9/48 ,  G06K9/6204 ,  G06T7/2033 ,  G06T9/001 ,  G06K2009/484

摘要： An apparatus for comparing a data pattern with standard patterns to discriminate the data pattern retrieves vector series of the standard patterns associated with the data pattern. Categorized names are assigned to data of the vector series so as to be respectively associated with elements of the data pattern, thereby determining a similarity degree and a scale factor between the vector series.

摘要翻译： 用于将数据模式与标准模式进行比较以区分数据模式的装置检索与数据模式相关联的标准模式的向量序列。 将分类的名称分配给矢量序列的数据，以分别与数据模式的元素相关联，从而确定矢量序列之间的相似度和比例因子。

公开(公告)号：US20050041316A1

公开(公告)日：2005-02-24

申请号：US10914243

申请日：2004-08-10

申请人： Takatoshi Kato ,  Takushi Nishiya ,  Hideyuki Yamakawa ,  Takashi Nara ,  Nobuaki Nakai ,  Hiroshi Ide ,  Shintaro Suzumura ,  Terumi Takashi

发明人： Takatoshi Kato ,  Takushi Nishiya ,  Hideyuki Yamakawa ,  Takashi Nara ,  Nobuaki Nakai ,  Hiroshi Ide ,  Shintaro Suzumura ,  Terumi Takashi

IPC分类号： G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/14 ,  G11B20/20

CPC分类号： G11B20/10009 ,  G11B5/012 ,  G11B5/09 ,  G11B20/1403

摘要： In order to generate a sampling clock having a higher accuracy, a synchronous signal generating circuit is provided with a phase error detector, detecting a phase error of a read out signal digitized on the basis of FDTS algorithm, and a VCO, controlling an oscillation frequency on the basis of a phase error detected by the phase error detector, to generate a synchronous signal by the VCO. On the basis of the synchronous signal generated by the synchronous signal generating circuit, an ADC digitizes the read out signal. The digitized read out signal is then converted to binary data by a detection circuit.

公开(公告)号：US5844741A

公开(公告)日：1998-12-01

申请号：US548956

申请日：1995-10-27

申请人： Hideyuki Yamakawa ,  Takushi Nishiya ,  Takashi Nara ,  Terumi Takashi

发明人： Hideyuki Yamakawa ,  Takushi Nishiya ,  Takashi Nara ,  Terumi Takashi

IPC分类号： G11B20/14 ,  G11B5/012 ,  G11B5/09 ,  G11B20/10 ,  G11B20/18 ,  H03M13/23 ,  H04L25/08 ,  H04L25/497 ,  G11B5/035

CPC分类号： G11B20/10175 ,  G11B20/10009 ,  G11B5/012 ,  G11B5/09

摘要： A system for reproducing data recorded on a magnetic recording medium at high density is provided as a simple configuration. Quadripartite reproduction data is output from a Viterbi detection circuit to an adder, which then subtracts the quadripartite reproduction data from a signal before PR4-ML method data determination. An adder is used to perform a (1+D) process for the result. An error signal pattern detection circuit performs maximum likelihood estimation for an PR4-ML method detection error. Further, when a detected determination error matches an actual reproduction data string, a data correction circuit corrects the reproduction data string.

摘要翻译： 作为简单的结构，提供了以高密度再现记录在磁记录介质上的数据的系统。 四维重放数据从维特比检测电路输出到加法器，然后从PR4-ML方法数据确定之前的信号中减去四方再生数据。 使用加法器对结果执行（1 + D）处理。 误差信号图案检测电路对PR4-ML方法检测误差进行最大似然估计。 此外，当检测到的确定错误与实际再现数据串匹配时，数据校正电路校正再现数据串。

公开(公告)号：US5265222A

公开(公告)日：1993-11-23

申请号：US617347

申请日：1990-11-23

申请人： Takushi Nishiya ,  Motohisa Funabashi ,  Hiromitsu Kurisu ,  Mikio Yoda ,  Kazuo Kera

发明人： Takushi Nishiya ,  Motohisa Funabashi ,  Hiromitsu Kurisu ,  Mikio Yoda ,  Kazuo Kera

IPC分类号： G05B13/02 ,  G06F9/44 ,  G06N3/04 ,  G06N7/02 ,  G06F15/18 ,  G05B19/06 ,  G06F15/46

CPC分类号： G06N3/0436 ,  G06N7/023 ,  Y10S706/90 ,  Y10S706/906

摘要： A symbolization apparatus which includes a membership function memory unit for storing a membership function used in fuzzy logic processing. In the symbolization apparatus a process condition change pattern is converted into an ambiguous symbol in order to build up a system capable of effecting an inference and decision approximate to a skilled operator against an object process. A process condition value memory is disclosed for holding a measurement of the process condition value and a process operation amount, a control history memory unit for storing operations and values converted into symbolic expressions, control units and a knowledge base for storing the information relating to the casual relations between the process control values and the process conditions. The process control system and a control support system comprise the function of condition identification approximate to that of a skilled operator by the use of the symbolization apparatus.

摘要翻译： 一种符号化装置，包括用于存储在模糊逻辑处理中使用的隶属函数的隶属函数存储单元。 在符号化装置中，处理条件改变模式被转换为不明确的符号，以建立能够对熟练的操作者进行对象处理的能够进行推理和判定的系统。 公开了一种用于保持处理条件值和处理操作量的测量的处理条件值存储器，用于存储转换为符号表达式的操作和值的控制历史存储单元，控制单元和用于存储与 过程控制值与过程条件之间的随机关系。 过程控制系统和控制支持系统通过使用符号化装置来构成与熟练操作者相近的条件识别功能。