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    Electrically erasable and programmable semiconductor memory
    1.
    发明授权
    Electrically erasable and programmable semiconductor memory 有权
    电可擦除和可编程的半导体存储器

    公开(公告)号：US06337807B2

    公开(公告)日：2002-01-08

    申请号：US09749737

    申请日：2000-12-28

    申请人： Takuya Futatsuyama ,  Kenichi Imamiya ,  Tamio Ikehashi

    发明人： Takuya Futatsuyama ,  Kenichi Imamiya ,  Tamio Ikehashi

    IPC分类号： G11C1604

    CPC分类号： G11C16/08

    摘要： A first transistor is connected between the gates of select transistors connected to two ends of a memory cell and a select line control circuit. A first gate line is connected to the gate of the first transistor. A first voltage control circuit controls the voltage of the first gate line to turn on or off the first transistor. A second transistor is connected between the control gate of the memory cell and a word line control circuit. A second gate line separated from the first gate line is connected to the gate of the second transistor. A second voltage control circuit controls the voltage of the second gate line to turn on or off the second transistor.

    摘要翻译： 第一晶体管连接在连接到存储单元的两端的选择晶体管的栅极和选择线控制电路之间。 第一栅极线连接到第一晶体管的栅极。 第一电压控制电路控制第一栅极线的电压以接通或关断第一晶体管。 第二晶体管连接在存储单元的控制栅极和字线控制电路之间。 与第一栅极线分离的第二栅极线连接到第二晶体管的栅极。 第二电压控制电路控制第二栅极线的电压以接通或关闭第二晶体管。

    Semiconductor memory device including page latch circuit
    3.
    发明申请
    Semiconductor memory device including page latch circuit 有权
    半导体存储器件包括页锁存电路

    公开(公告)号：US20050052930A1

    公开(公告)日：2005-03-10

    申请号：US10968303

    申请日：2004-10-20

    申请人： Junichiro Noda ,  Tamio Ikehashi ,  Kenichi Imamiya

    发明人： Junichiro Noda ,  Tamio Ikehashi ,  Kenichi Imamiya

    IPC分类号： G11C29/02 ,  G11C11/34

    CPC分类号： G11C29/02

    摘要： A semiconductor memory device having a data latch circuit has plural bit lines to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit latching the data transferred on the data bus, a read out circuit connected to the data bus, and a data transfer circuit group to directly transfer the data latched in the latch circuit to the read out circuit without transferring it to the memory cell.

    摘要翻译： 具有数据锁存电路的半导体存储器件具有连接有可再编程存储单元的多个位线，数据总线上传送数据，锁存电路锁存数据总线上传送的数据，读出电路连接到 数据总线和数据传输电路组，将锁存在锁存电路中的数据直接传送到读出电路，而不将其传送到存储单元。

    Semiconductor integrated circuit
    4.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US06674318B2

    公开(公告)日：2004-01-06

    申请号：US10231082

    申请日：2002-08-30

    申请人： Kazushige Kanda ,  Tamio Ikehashi ,  Ken Takeuchi ,  Kenichi Imamiya

    发明人： Kazushige Kanda ,  Tamio Ikehashi ,  Ken Takeuchi ,  Kenichi Imamiya

    IPC分类号： G05F110

    CPC分类号： G11C7/062

    摘要： A semiconductor integrated circuit includes a limiter circuit for outputting a voltage determining flag in order to set a boosted voltage level of a booster circuit to be a predetermined value, and a monitoring circuit for monitoring a monitoring node of the limiter circuit to output a monitoring signal for the stabilization of a boosted voltage to a first external terminal. The monitoring circuit detects a first level change of the voltage determining flag from “H” to “L” after the starting of the operation of the limiter circuit, by means of a comparator, to which an external power supply voltage and external reference voltage supplied from second and third external terminals are given, and thereafter, outputs a monitoring signal for holding a constant logical level during the operation of the limiter circuit. In order to provide a voltage trimming function, a voltage intended to be set in an external terminal may be given from the outside to deactivate a feedback system of the limiter circuit to operate a resistance value of the limiter circuit to detect and store a limiter flag. Thus, there is provided a semiconductor integrated circuit capable of simply monitoring the output voltage state of an internal power supply circuit by the external terminal and easily trimming an internal voltage.

    摘要翻译： 半导体集成电路包括限幅电路，用于输出电压确定标志，以便将升压电路的升压电压设定为预定值;以及监视电路，用于监视限幅器电路的监视节点以输出监视信号 用于稳定第一外部端子的升压电压。 监控电路通过比较器检测在限制器电路的操作开始之后电压确定标志从“H”到“L”的第一电平变化，供给外部电源电压和外部参考电压 给出第二和第三外部端子，然后在限幅器电路的操作期间输出用于保持恒定逻辑电平的监视信号。 为了提供电压调整功能，可以从外部给出旨在设置在外部端子中的电压以去激活限幅器电路的反馈系统，以操作限幅器电路的电阻值以检测和存储限幅器标志 。 因此，提供了能够简单地通过外部端子监视内部电源电路的输出电压状态并容易地修整内部电压的半导体集成电路。

    Fail number detecting circuit of flash memory
    7.
    发明授权
    Fail number detecting circuit of flash memory 有权
    闪存的故障号检测电路

    公开(公告)号：US06859401B2

    公开(公告)日：2005-02-22

    申请号：US10674404

    申请日：2003-10-01

    申请人： Koji Hosono ,  Tamio Ikehashi ,  Tomoharu Tanaka ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi

    发明人： Koji Hosono ,  Tamio Ikehashi ,  Tomoharu Tanaka ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi

    IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06 ,  G11C16/34 ,  G11C29/04 ,  G11C29/12

    CPC分类号： G11C16/3445 ,  G11C16/3436 ,  G11C16/3459

    摘要： A semiconductor device includes a memory cell array, latch circuits, first to third circuits and a current control circuit. The memory cell array includes NAND cells arranged therein. The latch circuits temporarily hold data read out from the memory cell array. The first circuit generates a first current varying in proportion to “1” or “0” of binary logic data of one end of the plurality of latch circuits. The second circuit generates a second current which is preset. The third circuit compares the first current with the second current. The value of “1” or “0” of binary logic data of the one end of the plurality of latch circuits is detected based on a result of the comparison between the first current and the second current.

    摘要翻译： 半导体器件包括存储单元阵列，锁存电路，第一至第三电路和电流控制电路。 存储单元阵列包括其中布置的NAND单元。 锁存电路暂时保存从存储单元阵列读出的数据。 第一电路产生与多个锁存电路的一端的二进制逻辑数据的“1”或“0”成比例变化的第一电流。 第二电路产生预置的第二电流。 第三电路将第一电流与第二电流进行比较。 基于第一电流和第二电流之间的比较结果，检测多个锁存电路一端的二进制逻辑数据的“1”或“0”值。

    Read circuit of nonvolatile semiconductor memory
    8.
    发明授权
    Read circuit of nonvolatile semiconductor memory 失效
    非易失性半导体存储器的读电路

    公开(公告)号：US06845047B2

    公开(公告)日：2005-01-18

    申请号：US10665019

    申请日：2003-09-22

    申请人： Tamio Ikehashi ,  Kenichi Imamiya ,  Junichiro Noda

    发明人： Tamio Ikehashi ,  Kenichi Imamiya ,  Junichiro Noda

    IPC分类号： G11C16/06 ,  G11C7/06 ,  G11C8/02 ,  G11C16/28 ,  G11C11/00

    CPC分类号： G11C7/067 ,  G11C7/062 ,  G11C16/28

    摘要： An INVSRC node and a SAREF node are previously precharged. After a potential on a bit line is reset, the bit line (BLS node) is precharged. In this event, a clamp MOS transistor in a sense amplifier is in ON state, and an SA node is also precharged simultaneously. A precharge level is set to a value lower than a threshold voltage of an inverter. Subsequently, when SAEN transitions to “H,” a sense operation is performed. For reading data “0,” the SA node is rapidly increased to Vdd. For reading data “1,” the SA node slowly approaches to Vss. A change in the potential at the SA node is detected by the inverter.

    摘要翻译： INVSRC节点和SAREF节点之前预充电。 在位线上的电位复位后，位线（BLS节点）被预充电。 在这种情况下，读出放大器中的钳位MOS晶体管处于导通状态，并且SA节点也被同时预充电。 预充电电平被设定为低于逆变器的阈值电压的值。 随后，当SAEN转换到“H”时，执行感测操作。 为了读取数据“0”，SA节点迅速增加到Vdd。 为了读取数据“1”，SA节点缓慢接近Vss。 变频器检测出SA节点的电位变化。

    Semiconductor memory device including page latch circuit
    9.
    发明授权
    Semiconductor memory device including page latch circuit 有权
    半导体存储器件包括页锁存电路

    公开(公告)号：US06826116B2

    公开(公告)日：2004-11-30

    申请号：US10751463

    申请日：2004-01-06

    申请人： Junichiro Noda ,  Tamio Ikehashi ,  Kenichi Imamiya

    发明人： Junichiro Noda ,  Tamio Ikehashi ,  Kenichi Imamiya

    IPC分类号： G11C700

    CPC分类号： G11C29/02

    摘要： A semiconductor memory device having a data latch circuit has plural bit lines to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit latching the data transferred on the data bus, a read out circuit connected to the data bus, and a data transfer circuit group to directly transfer the data latched in the latch circuit to the read out circuit without transferring it to the memory cell.

    摘要翻译： 具有数据锁存电路的半导体存储器件具有连接有可再编程存储单元的多个位线，数据总线上传送数据，锁存电路锁存数据总线上传送的数据，读出电路连接到 数据总线和数据传输电路组，将锁存在锁存电路中的数据直接传送到读出电路，而不将其传送到存储单元。

    Fail number detecting circuit of flash memory
    10.
    发明授权
    Fail number detecting circuit of flash memory 有权
    闪存的故障号检测电路

    公开(公告)号：US06657896B2

    公开(公告)日：2003-12-02

    申请号：US10315050

    申请日：2002-12-10

    申请人： Koji Hosono ,  Tamio Ikehashi ,  Tomoharu Tanaka ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi

    发明人： Koji Hosono ,  Tamio Ikehashi ,  Tomoharu Tanaka ,  Kenichi Imamiya ,  Hiroshi Nakamura ,  Ken Takeuchi

    IPC分类号： G11C1606

    CPC分类号： G11C16/3445 ,  G11C16/3436 ,  G11C16/3459

    摘要： A semiconductor memory device includes a memory cell array, latch circuits, first to third circuits and a current control circuit. The memory cell array includes electrically rewritable nonvolatile memory cells arranged therein. The latch circuits temporarily hold data read out from the memory cell array. The first circuit generates a first current which varies in proportion to “1” or “0” of binary logical data of one end of the latch circuits. The second circuit generates a predetermined second current. The current control circuit is connected to the first and second circuits, and configured to determined absolute values of the first and second currents. The third circuit is configured to compare the first and second currents. The number of binary logical data of “1” or “0” of one end of the latch circuits is detected based on the result of comparison between the first and second currents.

    摘要翻译： 半导体存储器件包括存储单元阵列，锁存电路，第一至第三电路和电流控制电路。 存储单元阵列包括布置在其中的电可重写非易失性存储单元。 锁存电路暂时保存从存储单元阵列读出的数据。 第一电路产生与锁存电路的一端的二进制逻辑数据的“1”或“0”成比例变化的第一电流。 第二电路产生预定的第二电流。 电流控制电路连接到第一和第二电路，并被配置为确定第一和第二电流的绝对值。 第三电路被配置为比较第一和第二电流。 基于第一和第二电流之间的比较结果来检测锁存电路的一端的“1”或“0”的二进制逻辑数据的数量。