公开(公告)号：US07684270B2

公开(公告)日：2010-03-23

申请号：US11892488

申请日：2007-08-23

申请人： Takuya Hirota ,  Takao Yanagida ,  Hiroyuki Takahashi

发明人： Takuya Hirota ,  Takao Yanagida ,  Hiroyuki Takahashi

IPC分类号： G11C7/02

CPC分类号： G11C11/4094 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2281

摘要： In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit (50) which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N1) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD−Va) and a second transistor (N2) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuit 50 makes the first transistor (N1) conductive, and then makes the second transistor (N2) conductive.

摘要翻译： 在传统的均衡器电路中，在将具有预定电压差的布线对的电压设定为相同的均衡操作中，使配线的电压成对地收敛到具有偏移的电压需要很长时间 相对于均衡动作后的配线对的电压的中点电压。 根据本发明的均衡器电路，提供了将第一布线（SAP）和第二布线（SAN）的电压设置为基本相同的并具有第一晶体管（N1）的均衡器电路（50） 连接在第一布线（SAP）和连接在第一布线SAP和第二布线（SAN）之间的第一电源电路（例如，HVDD-Va）和第二晶体管（N2）之间。 均衡器电路50使第一晶体管（N1）导通，然后使第二晶体管（N2）导通。

公开(公告)号：US07489576B2

公开(公告)日：2009-02-10

申请号：US11723830

申请日：2007-03-22

申请人： Takuya Hirota ,  Takao Yanagida

发明人： Takuya Hirota ,  Takao Yanagida

IPC分类号： G11C7/02

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/065

摘要： A semiconductor storage device has first and second cell arrays including a plurality of memory cells to store data, a sense amplifier selectively connected with either one of the first and second cell arrays, a first precharge circuit to set a pair of bit lines in the first cell array to a predetermined voltage, a second precharge circuit to set a pair of bit lines in the second cell array to a predetermined voltage, a first switch circuit to connect the sense amplifier with the first cell array, a second switch circuit to connect the sense amplifier with the second cell array, and a switch controller to control conductive state of the first and second switch circuits. In non-selection state where the sense amplifier does not access any of the cell arrays, the switch controller controls one of the switch circuits into conducting state.

摘要翻译： 一种半导体存储装置具有包括存储数据的多个存储单元的第一和第二单元阵列，选择性地与第一和第二单元阵列中的任一个连接的读出放大器，第一预充电电路，用于在第一和第二单元阵列中设置一对位线 单元阵列到预定电压，第二预充电电路，用于将第二单元阵列中的一对位线设置为预定电压;第一开关电路，用于将读出放大器与第一单元阵列连接;第二开关电路， 具有第二单元阵列的读出放大器和用于控制第一和第二开关电路的导通状态的开关控制器。 在非选择状态，其中读出放大器不访问任何单元阵列，开关控制器将开关电路之一控制为导通状态。

公开(公告)号：US20090016123A1

公开(公告)日：2009-01-15

申请号：US12168986

申请日：2008-07-08

申请人： Takao Yanagida ,  Takuya Hirota

发明人： Takao Yanagida ,  Takuya Hirota

IPC分类号： G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/1006 ,  G11C7/1009 ,  G11C11/4096

摘要： A semiconductor device (DRAM) according to one embodiment of the present invention includes a plurality of pairs of digit lines (digit True, Not) connected to a memory cell, a common signal line pair (main I/O True, Not) connected to the plurality of pairs of digit lines in common, a main I/O equalizer performing precharge of the common signal line pair, and a control circuit determining whether the precharge operation is continued irrespective of a signal level of a mask signal input from an outside.

摘要翻译： 根据本发明的一个实施例的半导体器件（DRAM）包括连接到存储器单元的多对数字线（数字True，Not），连接到存储单元的公共信号线对（主I / O True，否） 多个数字线对，主I / O均衡器，执行公共信号线对的预充电，以及控制电路，确定预充电操作是否继续，而与外部输入的屏蔽信号的信号电平无关。

公开(公告)号：US20070223297A1

公开(公告)日：2007-09-27

申请号：US11723830

申请日：2007-03-22

申请人： Takuya Hirota ,  Takao Yanagida

发明人： Takuya Hirota ,  Takao Yanagida

IPC分类号： G11C7/00 ,  G11C7/02

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2207/005 ,  G11C2207/065

摘要： A semiconductor storage device has first and second cell arrays including a plurality of memory cells to store data, a sense amplifier selectively connected with either one of the first and second cell arrays, a first precharge circuit to set a pair of bit lines in the first cell array to a predetermined voltage, a second precharge circuit to set a pair of bit lines in the second cell array to a predetermined voltage, a first switch circuit to connect the sense amplifier with the first cell array, a second switch circuit to connect the sense amplifier with the second cell array, and a switch controller to control conductive state of the first and second switch circuits. In non-selection state where the sense amplifier does not access any of the cell arrays, the switch controller controls one of the switch circuits into conducting state.

摘要翻译： 一种半导体存储装置具有包括存储数据的多个存储单元的第一和第二单元阵列，选择性地与第一和第二单元阵列中的任一个连接的读出放大器，第一预充电电路，用于在第一和第二单元阵列中设置一对位线 单元阵列到预定电压，第二预充电电路，用于将第二单元阵列中的一对位线设置为预定电压;第一开关电路，用于将读出放大器与第一单元阵列连接;第二开关电路， 具有第二单元阵列的读出放大器和用于控制第一和第二开关电路的导通状态的开关控制器。 在非选择状态，其中读出放大器不访问任何单元阵列，开关控制器将开关电路之一控制为导通状态。

公开(公告)号：US08045409B2

公开(公告)日：2011-10-25

申请号：US12603879

申请日：2009-10-22

申请人： Takuya Hirota ,  Takao Yanagida

发明人： Takuya Hirota ,  Takao Yanagida

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C11/41 ,  G11C29/12 ,  G11C29/50 ,  G11C2029/1204 ,  G11C2029/5006

摘要： A semiconductor memory device includes a plurality of memory cells that are arranged at intersections of a word line with bit line pairs, a precharge circuit that is arranged for each of the bit line pairs and is configured to precharge each of the bit line pairs, and a Y-switch circuit that is arranged for each of the bit line pairs and is configured to select each of the bit line pairs. The semiconductor memory device further includes a mode switching unit that switches the normal mode and the test mode in accordance with a mode selection signal that is externally supplied, a plurality of individual control units that control operation of each of the precharge circuits in accordance with operation of each of the Y-switch circuits in the normal mode, and a block control unit that collectively turns off all of the precharge circuits in the test mode.

摘要翻译： 半导体存储器件包括布置在字线与位线对的交点处的多个存储器单元，为每个位线对布置的预充电电路，并且被配置为对每个位线对进行预充电;以及 一个Y开关电路，其被布置用于每个位线对并被配置为选择每个位线对。 半导体存储装置还包括模式切换单元，其根据外部提供的模式选择信号切换正常模式和测试模式，多个单独控制单元，其根据操作控制每个预充电电路的操作 的正常模式中的Y开关电路，以及在测试模式下共同地关闭所有预充电电路的块控制单元。

公开(公告)号：US20100103756A1

公开(公告)日：2010-04-29

申请号：US12603879

申请日：2009-10-22

申请人： Takuya HIROTA ,  Takao Yanagida

发明人： Takuya HIROTA ,  Takao Yanagida

IPC分类号： G11C7/00 ,  G11C11/00 ,  G11C7/10

CPC分类号： G11C7/12 ,  G11C11/41 ,  G11C29/12 ,  G11C29/50 ,  G11C2029/1204 ,  G11C2029/5006

摘要： A semiconductor memory device includes a plurality of memory cells that are arranged at intersections of a word line with bit line pairs, a precharge circuit that is arranged for each of the bit line pairs and is configured to precharge each of the bit line pairs, and a Y-switch circuit that is arranged for each of the bit line pairs and is configured to select each of the bit line pairs. The semiconductor memory device further includes a mode switching unit that switches the normal mode and the test mode in accordance with a mode selection signal that is externally supplied, a plurality of individual control units that control operation of each of the precharge circuits in accordance with operation of each of the Y-switch circuits in the normal mode, and a block control unit that collectively turns off all of the precharge circuits in the test mode.

摘要翻译： 半导体存储器件包括布置在字线与位线对的交点处的多个存储器单元，为每个位线对布置的预充电电路，并且被配置为对每个位线对进行预充电;以及 一个Y开关电路，其被布置用于每个位线对并被配置为选择每个位线对。 半导体存储装置还包括模式切换单元，其根据外部提供的模式选择信号切换正常模式和测试模式，多个单独控制单元，其根据操作控制每个预充电电路的操作 的正常模式中的Y开关电路，以及在测试模式下共同地关闭所有预充电电路的块控制单元。

公开(公告)号：US07692988B2

公开(公告)日：2010-04-06

申请号：US12168986

申请日：2008-07-08

申请人： Takao Yanagida ,  Takuya Hirota

发明人： Takao Yanagida ,  Takuya Hirota

IPC分类号： G11C7/00

CPC分类号： G11C11/4076 ,  G11C7/1006 ,  G11C7/1009 ,  G11C11/4096

摘要： A semiconductor device (DRAM) according to one embodiment of the present invention includes a plurality of pairs of digit lines (digit True, Not) connected to a memory cell, a common signal line pair (main I/O True, Not) connected to the plurality of pairs of digit lines in common, a main I/O equalizer performing precharge of the common signal line pair, and a control circuit determining whether the precharge operation is continued irrespective of a signal level of a mask signal input from an outside.

摘要翻译： 根据本发明的一个实施例的半导体器件（DRAM）包括连接到存储器单元的多对数字线（数字True，Not），连接到存储单元的公共信号线对（主I / O True，否） 多个数字线对，主I / O均衡器，执行公共信号线对的预充电，以及控制电路，确定预充电操作是否继续，而与外部输入的屏蔽信号的信号电平无关。

公开(公告)号：US20080049530A1

公开(公告)日：2008-02-28

申请号：US11892488

申请日：2007-08-23

申请人： Takuya Hirota ,  Takao Yanagida ,  Hiroyuki Takahashi

发明人： Takuya Hirota ,  Takao Yanagida ,  Hiroyuki Takahashi

IPC分类号： G11C11/4091 ,  G05F1/00

CPC分类号： G11C11/4094 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/22 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2281

摘要： In a conventional equalizer circuit, in an equalizing operation for setting voltages of a wiring pair having a predetermined voltage difference therebetween to be the same, it takes a long time to make the voltages of the wirings in a pair converge to a voltage having an offset with respect to a midpoint voltage of the voltages of the wiring pair after the equalizing operation. According to an equalizer circuit of the present invention, provided is an equalizer circuit (50) which sets the voltages of a first wiring (SAP) and a second wiring (SAN) to be substantially the same and which has a first transistor (N1) connected between the first wiring (SAP) and a first power supply circuit (for example, HVDD−Va) and a second transistor (N2) connected between the first wiring SAP and the second wiring (SAN). The equalizer circuit 50 makes the first transistor (N1) conductive, and then makes the second transistor (N2) conductive.

摘要翻译： 在传统的均衡器电路中，在将具有预定电压差的布线对的电压设定为相同的均衡操作中，使配线的电压成对地收敛到具有偏移的电压需要很长时间 相对于均衡动作后的配线对的电压的中点电压。 根据本发明的均衡器电路，提供了一种均衡器电路（50），其将第一布线（SAP）和第二布线（SAN）的电压设置为基本相同，并且具有第一晶体管（N 1 ）连接在第一布线（SAP）和第一电源电路（例如，HVDD-Va）之间，第二晶体管（N 2）连接在第一布线SAP和第二布线（SAN）之间。 均衡电路50使第一晶体管（N1）导通，然后使第二晶体管（N 2）导通。

公开(公告)号：US07573273B2

公开(公告)日：2009-08-11

申请号：US11440071

申请日：2006-05-25

申请人： Takao Yanagida

发明人： Takao Yanagida

IPC分类号： G01R31/02

CPC分类号： G11C17/18 ,  G11C29/02 ,  G11C29/027

摘要： A fuse cutting test method to test the state of a fuse includes measuring the current flowing through the fuse and determining the fuse to be either broken, or not broken, or in a state therebetween, based on the measured current.

摘要翻译： 用于测试熔丝状态的熔丝切割测试方法包括测量流过熔丝的电流，并基于所测量的电流来确定熔丝被破坏或不断裂，或者处于它们之间的状态。

公开(公告)号：US20060268485A1

公开(公告)日：2006-11-30

申请号：US11440071

申请日：2006-05-25

申请人： Takao Yanagida

发明人： Takao Yanagida

IPC分类号： H02H5/04

CPC分类号： G11C17/18 ,  G11C29/02 ,  G11C29/027

摘要： A fuse cutting test method to test the state of a fuse, comprises, measuring the current flowing through the fuse and determining the fuse to be either broken, or not broken, or in a state therebetween, based on the measured.

摘要翻译： 一种用于测试保险丝状态的保险丝切割测试方法，包括：测量流过保险丝的电流，并根据测量值确定保险丝断开或不断开或处于其间的状态。