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公开(公告)号：US5872733A
公开(公告)日：1999-02-16
申请号：US730628
申请日：1996-10-21
申请人： Taqi Nasser Buti , Louis Lu-Chen Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary Joseph Saccamango , Hyun Jong Shin
发明人： Taqi Nasser Buti , Louis Lu-Chen Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary Joseph Saccamango , Hyun Jong Shin
摘要： An apparatus for controlling the ramp-up rate of a charge pump having an output providing an output voltage and an output current. In one embodiment, the apparatus comprises a current bleeder circuit having an input, an output adapted for connection to ground potential and at least one transistor having a gate, source, drain and body and defining at least one current path between the source and drain to form a current path between the input and output. The body is adapted for connection to the charge pump output. The apparatus further comprises a control circuit having an input adapted for connection to the charge pump output and an output connected to the bleeder circuit input. The control circuit provides a voltage potential to the input of the current bleeder circuit to control the gate-to-source voltage of the current bleeder circuit transistor. The flow of current through the current path of the current bleeder path is a function of the magnitude of the charge pump output and the gate-to-source voltage of the bleeder circuit transistor. Other embodiments of the apparatus of the present invention are described herein.
摘要翻译： 一种用于控制具有提供输出电压和输出电流的输出的电荷泵的上升速率的装置。 在一个实施例中，该装置包括具有输入，适于连接到地电势的输出和至少一个具有栅极，源极，漏极和主体的晶体管的电流泄放电路，并且限定源极和漏极之间的至少一个电流路径 形成输入和输出之间的当前路径。 主体适用于连接到电荷泵输出。 该装置还包括具有适于连接到电荷泵输出的输入端的控制电路和连接到泄放电路输入端的输出端。 控制电路为电流放电电路的输入提供电压电位，以控制电流放电电路晶体管的栅极 - 源极电压。 通过电流泄放路径的电流路径的电流流动是电荷泵输出的大小和泄放电路晶体管的栅极 - 源极电压的函数。 本文描述了本发明装置的其它实施例。
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公开(公告)号：US5736891A
公开(公告)日：1998-04-07
申请号：US585336
申请日：1996-01-11
申请人： Taqi Nasser Buti , Louis Lu-Chen Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary J. Saccamango , Hyun Jong Shin
发明人： Taqi Nasser Buti , Louis Lu-Chen Hsu , Jente B. Kuang , Somnuk Ratanaphanyarat , Mary J. Saccamango , Hyun Jong Shin
IPC分类号： G11C16/30 , H03K17/10 , H03K17/687
CPC分类号： H03K17/102 , G11C16/30 , H03K17/6872
摘要： A discharge circuit for a semiconductor memory includes a first node, a second node for receiving a control signal having first and second states, and a circuit connected between the first node and ground potential and to the second node. The circuit couples the first node to ground potential when the control signal has the first state and substantially isolates the first node from ground potential when the control signal has the second state. The circuit includes a first subcircuit for defining a current path between the first node and ground potential. The first subcircuit includes a plurality of transistors connected in series, each of which having a gate, source and drain. The circuit further includes a second subcircuit for effecting predetermined gate-to-source, and drain-to-source voltages of the transistors of the first subcircuit when the control signal has the second state.
摘要翻译： 用于半导体存储器的放电电路包括第一节点，用于接收具有第一和第二状态的控制信号的第二节点和连接在第一节点和地电位之间的电路以及连接到第二节点的电路。 当控制信号具有第一状态时，电路将第一节点耦合到地电位，并且当控制信号具有第二状态时，电路基本上将第一节点与地电势隔离。 电路包括用于限定第一节点和地电位之间的电流路径的第一子电路。 第一分支电路包括串联连接的多个晶体管，每个晶体管具有栅极，源极和漏极。 当控制信号具有第二状态时，电路还包括用于实现第一子电路的晶体管的预定栅极至源极和漏极至源极电压的第二子电路。
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公开(公告)号：US6151200A
公开(公告)日：2000-11-21
申请号：US452934
申请日：1999-12-02
CPC分类号： H02H9/046
摘要： Apparatus and method for discharging the body of a monitored SOI device through first and second discharge circuits. The second discharge circuit is selectively activated when the body potential of the monitored SOI device is at a level such that the body charge of the monitored SOI device cannot be discharged entirely through the first discharge circuit within normal operating cycle time allowances.
摘要翻译： 通过第一和第二放电电路对被监测的SOI器件的体放电的装置和方法。 当所监视的SOI器件的体电位处于使得所监视的SOI器件的体电量在正常工作周期时间容限内不能通过第一放电电路完全放电的水平时，选择性地激活第二放电电路。
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公开(公告)号：US6078058A
公开(公告)日：2000-06-20
申请号：US35407
申请日：1998-03-05
IPC分类号： H02H9/04 , H01L23/58 , H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H02H9/046
摘要： Apparatus and method for discharging the body of a monitored SOI device through first and second discharge circuits. The second discharge circuit is selectively activated when the body potential of the monitored SOI device is at a level such that the body charge of the monitored SOI device cannot be discharged entirely through the first discharge circuit within normal operating cycle time allowances.
摘要翻译： 通过第一和第二放电电路对被监测的SOI器件的体放电的装置和方法。 当所监视的SOI器件的体电位处于使得所监视的SOI器件的体电量在正常工作周期时间容限内不能通过第一放电电路完全放电的水平时，选择性地激活第二放电电路。
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公开(公告)号：US20130077415A1
公开(公告)日：2013-03-28
申请号：US13247362
申请日：2011-09-28
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/02 , G11C7/04 , G11C11/417 , G11C11/419
摘要： An apparatus and method for combating the effects of bias temperature instability (BTI) in a memory cell. Bit lines connecting to a memory cell contain two alternate paths criss-crossing to connect a lower portion of a first bit line to an upper portion of a second bit line, and to connect a lower portion of the second bit line to an upper portion of the first bit line. Alternative to activating transistors on the bit lines to read and write to the memory cell, transistors on the alternative paths may be activated to read and write to the memory cell from the opposite bit lines. The memory cell may be read through the bit lines to a sense amplifier, the transistors on the bit lines are subsequently deactivated and the transistors on the alternate paths are activated to write transposed bit values to the memory cell, thereby reversing the biases.
摘要翻译： 一种用于抵抗存储单元中偏置温度不稳定性（BTI）的影响的装置和方法。 连接到存储器单元的位线包含两个交替的交替路径，以将第一位线的下部连接到第二位线的上部，并且将第二位线的下部连接到第二位线的上部 第一个位线。 在位线上激活晶体管以读取和写入存储器单元的替代方案是替代路径上的晶体管可被激活以从相对的位线读取和写入存储器单元。 存储器单元可以通过位线读取到读出放大器，位线上的晶体管随后被去激活，并且激活交替路径上的晶体管以将转置的位值写入存储器单元，从而反转偏置。
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6.发明授权Optimizing SRAM performance over extended voltage or process range using self-timed calibration of local clock generator 有权使用本地时钟发生器的自定时校准优化扩展电压或过程范围内的SRAM性能公开(公告)号：US07864625B2
公开(公告)日：2011-01-04
申请号：US12244286
申请日：2008-10-02
CPC分类号： G11C11/417 , G11C7/22 , G11C11/419
摘要： A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In an application for a local clock buffer of a static, random-access memory (SRAM), the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. These voltages may vary in response to dynamic voltage scaling, requiring re-calibration of the adjustable delay path. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns the correct output, or by using a replica SRAM path to simulate variations in delay with changes in voltage supply.
摘要翻译： 延迟电路具有在较低电压电平的固定延迟路径，电平转换器和在较高电压电平下的可调延迟路径。 固定延迟路径包括反相器链，并且可调延迟路径包括选择性地连接到电路输出的串联连接的延迟元件。 在静态随机存取存储器（SRAM）的本地时钟缓冲器的应用中，较低的电压电平是本地时钟缓冲器的电平，而较高的电压电平是SRAM的电压电平。 这些电压可以响应于动态电压缩放而变化，需要重新校准可调延迟路径。 可调整的延迟路径可以通过逐渐增加SRAM阵列的读取访问时间来校准，直到同时读取操作返回正确的输出，或者通过使用复制SRAM路径来模拟延迟随电压变化的变化。
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公开(公告)号：US07847618B2
公开(公告)日：2010-12-07
申请号：US11970771
申请日：2008-01-08
申请人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
发明人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
IPC分类号： H03K3/01
CPC分类号： H02M3/073 , H02M2003/077 , H03L5/00
摘要： A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.
摘要翻译： 分布式电荷泵系统使用延迟元件和分频器产生驱动不同电荷泵的异相泵浦时钟信号，以抵消每个电荷泵的峰值电流时钟边缘，从而降低总体峰值功率。 时钟信号分频和相位偏移可以扩展到多个级别，以进一步平滑泵时钟信号转换。 可以使用双分频器，其接收时钟信号及其补码，并产生相位差为90°的两个分频信号。 在说明性实施例中，时钟发生器包括可变频率时钟源，并且电压调节器感测电荷泵的输出电压，基于当前选择的可变频率时钟源的频率产生参考电压，并暂时禁用 当输出电压大于参考电压时，电荷泵（通过关闭本地泵浦时钟）。
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公开(公告)号：US20100220541A1
公开(公告)日：2010-09-02
申请号：US12778960
申请日：2010-05-12
申请人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
发明人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
CPC分类号： H02M3/07 , G11C5/145 , G11C11/4074 , G11C2207/104
摘要： A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit advantageously utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors.
摘要翻译： 开关电容器电荷泵包括两相充电电路，连接到开关电容器的输出节点的交叉耦合晶体管和连接到交叉耦合晶体管的源极端子的泵浦输出。 电荷泵具有用于升压电荷转移的侧晶体管，并且侧晶体管的选通逻辑包括电平转换器，其控制与泵输出的连接或参考电压。 提供负电荷泵和正电荷泵实施例。 充电电路有利地利用非重叠的宽和窄的时钟信号来产生多个门控信号。 泵时钟电路优选地提供宽和窄时钟信号的宽度的独立的可编程调整。 可以使用将泵浦输出分流到开关电容器的第二节点的钳位电路来提供覆盖模式。
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公开(公告)号：US07760010B2
公开(公告)日：2010-07-20
申请号：US11927784
申请日：2007-10-30
申请人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
发明人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
CPC分类号： H02M3/07 , G11C5/145 , G11C11/4074 , G11C2207/104
摘要： A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit advantageously utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors.
摘要翻译： 开关电容器电荷泵包括两相充电电路，连接到开关电容器的输出节点的交叉耦合晶体管和连接到交叉耦合晶体管的源极端子的泵浦输出。 电荷泵具有用于升压电荷转移的侧晶体管，并且侧晶体管的选通逻辑包括电平转换器，其控制与泵输出的连接或参考电压。 提供负电荷泵和正电荷泵实施例。 充电电路有利地利用非重叠的宽和窄的时钟信号来产生多个门控信号。 泵时钟电路优选地提供宽和窄时钟信号的宽度的独立的可编程调整。 可以使用将泵浦输出分流到开关电容器的第二节点的钳位电路来提供覆盖模式。
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公开(公告)号：US07719315B2
公开(公告)日：2010-05-18
申请号：US11554666
申请日：2006-10-31
IPC分类号： H03K19/00
CPC分类号： G06F1/10 , G01R31/318552
摘要： A programmable clock generator circuit receives control signals and a global clock and generates a pulsed data clock and a scan clock in response to gating signals. The clock generator has data clock and scan clock feed-forward paths and a single feedback path. Delay control signals program delay elements in the feedback path and logic gates reshape and generate a feedback clock signal. The global clock and the feedback clock signal are combined to generates a pulsed local clock signal. A scan clock feed-forward circuit receives the local clock and generates the scan clock. A data clock feed-forward circuit receives the local clock and generates the data clock with a logic controlled delay relative to the local clock signal. The feedback clock is generated with controlled delay thereby modifying the pulse width of the data and scan clocks independent of the controlled delay of the data clock feed-forward path.
摘要翻译： 可编程时钟发生器电路接收控制信号和全局时钟，并响应门控信号产生脉冲数据时钟和扫描时钟。 时钟发生器具有数据时钟和扫描时钟前馈路径和单个反馈路径。 延迟控制信号在反馈路径中的程序延迟元件和逻辑门重新形成并产生反馈时钟信号。 全局时钟和反馈时钟信号被组合以产生脉冲本地时钟信号。 扫描时钟前馈电路接收本地时钟并产生扫描时钟。 数据时钟前馈电路接收本地时钟并产生相对于本地时钟信号的逻辑控制延迟的数据时钟。 以受控的延迟产生反馈时钟，从而修改数据的脉冲宽度和扫描时钟，而与数据时钟前馈路径的受控延迟无关。
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