公开(公告)号：US20080238733A1

公开(公告)日：2008-10-02

申请号：US12041395

申请日：2008-03-03

申请人： Tatsuhiro SUZUMURA ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Satoshi Takekawa ,  Masashi Jobashi ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Takaya Ogawa ,  Akihiro Oue

发明人： Tatsuhiro SUZUMURA ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Satoshi Takekawa ,  Masashi Jobashi ,  Hiromitsu Nakayama ,  Yoshinori Shigeta ,  Takaya Ogawa ,  Akihiro Oue

IPC分类号： H03M7/42

CPC分类号： H03M7/40 ,  H03M7/42 ,  H04N19/13

摘要： According to the present invention, there is provided an image decoding apparatus having: a table selection controller configured to output a syntax selection signal which selects one of a prefix level_prefix, a suffix level_suffix, and a TrailingOnes syntax; a variable-length code decoding device configured to receive a bit stream, the syntax selection signal, and a suffix length suffixLength, and, by using data contained in the bit stream and the suffix length suffixLength, simultaneously decode the prefix level_prefix and the suffix level_suffix and output the result if the syntax selection signal selects the prefix level_prefix and the suffix level_suffix, and decode the TrailingOnes syntax and output the result if the syntax selection signal selects the TrailingOnes syntax; a level formation device configured to receive the decoded prefix level_prefix, the decoded suffix level_suffix, and the decoded TrailingOnes syntax, and form and output a level; and a suffix length updating device configured to receive the decoded prefix level_prefix, the decoded suffix level_suffix, and the decoded TrailingOnes syntax, and update the suffix length suffixLength.

摘要翻译： 根据本发明，提供了一种图像解码装置，具有：表选择控制器，被配置为输出选择前缀level_prefix，后缀level_suffix和TrailingOnes语法之一的语法选择信号; 配置为接收比特流，语法选择信号和后缀长度suffixLength的可变长度码解码装置，并且通过使用包含在比特流和后缀长度suffixLength中的数据，同时解码前缀level_prefix和后缀level_suffix 并且如果语法选择信号选择前缀level_prefix和后缀level_suffix，并且如果语法选择信号选择TrailingOnes语法则解码TrailingOnes语法并输出结果，则输出结果; 电平形成装置，被配置为接收解码的前缀电平_prefix，解码的后缀电平补码和解码的TrailingOnes语法，并且形成并输出电平; 以及后缀长度更新装置，被配置为接收解码的前缀级别_refref，解码的后缀level_suffix和解码的TrailingOnes语法，并更新后缀长度suffixLength。

公开(公告)号：US20080137754A1

公开(公告)日：2008-06-12

申请号：US11857874

申请日：2007-09-19

申请人： Tatsuhiro SUZUMURA ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Masashi Jobashi ,  Takaya Ogawa ,  Hiromitsu Nakayama ,  Satoshi Takekawa ,  Yoshinori Shigeta ,  Akihiro Oue

发明人： Tatsuhiro SUZUMURA ,  Shuji Michinaka ,  Kiwamu Watanabe ,  Masashi Jobashi ,  Takaya Ogawa ,  Hiromitsu Nakayama ,  Satoshi Takekawa ,  Yoshinori Shigeta ,  Akihiro Oue

IPC分类号： H04N11/02

CPC分类号： H04N19/423 ,  H04N19/105 ,  H04N19/112 ,  H04N19/44 ,  H04N19/61

摘要： The image decoding apparatus and the image decoding method according to one aspect of the present invention have a configuration for storing an image decoded in the past as a reference picture into a frame memory, in a field structure in which top lines in the reference picture are stored in a top area and bottom lines in the reference picture are stored in a bottom area, in order to use a part of the image decoded in the past as a reference block in a picture being presently decoded; and selectively copying and storing an uppermost top line or an uppermost bottom line in the reference picture to areas on the uppermost top line and the uppermost bottom line in the reference picture in the top area and the bottom area in the frame memory, and selectively copying and storing a lowermost top line or a lowermost bottom line in the reference picture to areas under the lowermost top line and the lowermost bottom line in the reference picture in the top area and the bottom area in the frame memory.

摘要翻译： 根据本发明的一个方面的图像解码装置和图像解码方法具有将过去被解码为图像的图像作为参考图像存储到帧存储器中的结构，其中参考图像中的顶行是 存储在顶部区域中，参考图像中的底线存储在底部区域中，以便使用过去解码的图像的一部分作为当前解码的图像中的参考块; 并且将参考图像中的最上面的最上面的行或最上面的行选择性地复制并存储在帧存储器中的顶部区域和底部区域中的参考图像中的最上面的顶部行和最上面的底部的区域，并且选择性地复印 并且将参考图像中的最下顶行或最下底行存储在帧存储器中的顶区域和底区中的参考图片中的最下顶行和最​​下底行下方的区域。

公开(公告)号：US20120072650A1

公开(公告)日：2012-03-22

申请号：US13238357

申请日：2011-09-21

申请人： Tatsuhiro SUZUMURA ,  Kunihiko Yahagi

发明人： Tatsuhiro SUZUMURA ,  Kunihiko Yahagi

IPC分类号： G06F12/00

CPC分类号： G06F13/4243 ,  G06F13/1689 ,  Y02D10/14 ,  Y02D10/151

摘要： According to one embodiment, a DRAM controller includes a clock generating and switching unit for supplying a first clock to a DRAM in a normal operation and generating a second clock having a lower speed than the first clock and supplying the generated second clock to the DRAM in an initialization processing, and a DRAM access circuit having a DLL circuit for regulating a fetch timing of data output from the DRAM based on the first clock, and fetching, in a fetch timing regulated by the DLL circuit, data output from the DRAM in a timing based on the second clock in relation to the initialization processing and the transfer data output from the DRAM in a timing based on the first clock in the initialization processing and the normal processing, respectively.

摘要翻译： 根据一个实施例，DRAM控制器包括时钟发生和切换单元，用于在正常操作中向DRAM提供第一时钟，并产生具有比第一时钟低的速度的第二时钟，并将所产生的第二时钟提供给DRAM 初始化处理和具有DLL电路的DRAM访问电路，该DLL电路用于基于第一时钟调整从DRAM输出的数据的获取定时，并且在由DLL电路调节的获取定时中取出在DRAM中输出的数据 在初始化处理和正常处理的基础上，基于第一时钟的定时，分别基于关于初始化处理的第二时钟和从DRAM输出的传送数据的定时。

公开(公告)号：US20130173997A1

公开(公告)日：2013-07-04

申请号：US13685296

申请日：2012-11-26

申请人： Tatsuhiro SUZUMURA ,  Akira Yamaga

发明人： Tatsuhiro SUZUMURA ,  Akira Yamaga

IPC分类号： H03M13/03

CPC分类号： H03M13/03 ,  G06F11/1048

摘要： A memory controller includes a memory interface that has multiple channels and carries out writing into a nonvolatile memory through each of the channels, a data buffer, an ECC (error correcting code) encoder for applying an error correction encoding processing on write data which are to be written into the nonvolatile memory to generate ECC data, a channel allocation part for allocating the channels to the write data and the ECC data based on a write data format of the nonvolatile memory, a write data reception processing part that stores the write data in the data buffer and outputs the write data to the ECC encoder, and a channel scheduler for transferring the write data stored in the data buffer and the ECC data to the channels of the memory interface as allocated by the channel allocation part.

摘要翻译： 存储器控制器包括具有多个通道并通过每个通道执行写入非易失性存储器的存储器接口，数据缓冲器，用于对写入数据应用纠错编码处理的ECC（纠错码）编码器 写入非易失性存储器以产生ECC数据，用于基于非易失性存储器的写入数据格式将通道分配给写入数据的通道分配部分和ECC数据;写入数据接收处理部分， 数据缓冲器并将写入数据输出到ECC编码器，以及频道调度器，用于将存储在数据缓冲器中的写入数据和ECC数据传送到由信道分配部分分配的存储器接口的信道。

公开(公告)号：US20090279613A1

公开(公告)日：2009-11-12

申请号：US12407425

申请日：2009-03-19

申请人： Tatsuhiro SUZUMURA

发明人： Tatsuhiro SUZUMURA

IPC分类号： H04N7/26

CPC分类号： H04N19/436 ,  H04N19/176 ,  H04N19/44 ,  H04N19/46 ,  H04N19/61 ,  H04N19/70 ,  H04N19/91

摘要： A stream transmitting section outputs encoded stream data. A division instructing section generates dividing point information that designates a dividing point of the encoded stream data. A parallel stream transmitting section divides stream data that is output by the stream transmitting section and side information necessary for decoding from halfway along the stream that is extracted based on the stream data into a predetermined number of parts at dividing points designated by the dividing point information, performs parallelization thereof, and transmits data obtained as a result thereof to a stream decoding section on a receiving side.

摘要翻译： 流发送部输出编码流数据。 分区指令部分生成指定编码流数据的分割点的分割点信息。 并行流发送部分将由流发送部分输出的流数据和解码所需的侧信息沿着基于流数据提取的流中分割为由分割点信息指定的分割点处的预定数量的部分 执行其并行化，并将其结果获得的数据发送到接收侧的流解码部分。