公开(公告)号：US20120072650A1

公开(公告)日：2012-03-22

申请号：US13238357

申请日：2011-09-21

申请人： Tatsuhiro SUZUMURA ,  Kunihiko Yahagi

发明人： Tatsuhiro SUZUMURA ,  Kunihiko Yahagi

IPC分类号： G06F12/00

CPC分类号： G06F13/4243 ,  G06F13/1689 ,  Y02D10/14 ,  Y02D10/151

摘要： According to one embodiment, a DRAM controller includes a clock generating and switching unit for supplying a first clock to a DRAM in a normal operation and generating a second clock having a lower speed than the first clock and supplying the generated second clock to the DRAM in an initialization processing, and a DRAM access circuit having a DLL circuit for regulating a fetch timing of data output from the DRAM based on the first clock, and fetching, in a fetch timing regulated by the DLL circuit, data output from the DRAM in a timing based on the second clock in relation to the initialization processing and the transfer data output from the DRAM in a timing based on the first clock in the initialization processing and the normal processing, respectively.

摘要翻译： 根据一个实施例，DRAM控制器包括时钟发生和切换单元，用于在正常操作中向DRAM提供第一时钟，并产生具有比第一时钟低的速度的第二时钟，并将所产生的第二时钟提供给DRAM 初始化处理和具有DLL电路的DRAM访问电路，该DLL电路用于基于第一时钟调整从DRAM输出的数据的获取定时，并且在由DLL电路调节的获取定时中取出在DRAM中输出的数据 在初始化处理和正常处理的基础上，基于第一时钟的定时，分别基于关于初始化处理的第二时钟和从DRAM输出的传送数据的定时。

公开(公告)号：US08023565B2

公开(公告)日：2011-09-20

申请号：US11475172

申请日：2006-06-27

申请人： Tatsuhiro Suzumura ,  Akihiro Oue ,  Kunihiko Yahagi ,  Shuji Michinaka ,  Satoshi Takekawa ,  Kiwamu Watanabe

发明人： Tatsuhiro Suzumura ,  Akihiro Oue ,  Kunihiko Yahagi ,  Shuji Michinaka ,  Satoshi Takekawa ,  Kiwamu Watanabe

IPC分类号： H04N7/18

CPC分类号： H04N19/423 ,  H04N19/44 ,  H04N19/61

摘要： A picture processing apparatus includes a decoder configured to decode encoded data to generate a decoded picture. A picture memory has a plurality of banks each containing a plurality of pages to which row addresses are assigned, and is configured to store the decoded picture. A bank selector is configured to divide the decoded picture into a plurality of blocks, and to select a page of a different bank as a write location for a block adjacent in at least one of either a horizontal direction or a vertical direction. A write controller is configured to write pixel data of pixels occupying even lines of each of the blocks, and pixel data of pixels occupying odd lines of each of the blocks in a column address direction of each of the page in an alternating manner.

摘要翻译： 图像处理装置包括：解码器，被配置为对编码数据进行解码以生成解码图像。 图像存储器具有多个存储体，每个存储体包含分配了行地址的多个页面，并且被配置为存储解码图像。 存储体选择器被配置为将解码图像划分为多个块，并且选择不同存储体的页作为在水平方向或垂直方向中的至少一个中相邻的块的写入位置。 写入控制器被配置为写入占据每个块的偶数行的像素的像素数据，并且以交替的方式在每个页面的列地址方向上占据每个块的奇数行的像素的像素数据。

公开(公告)号：US20060291568A1

公开(公告)日：2006-12-28

申请号：US11475172

申请日：2006-06-27

申请人： Tatsuhiro Suzumura ,  Akihiro Oue ,  Kunihiko Yahagi ,  Shuji Michinaka ,  Satoshi Takekawa ,  Kiwamu Watanabe

发明人： Tatsuhiro Suzumura ,  Akihiro Oue ,  Kunihiko Yahagi ,  Shuji Michinaka ,  Satoshi Takekawa ,  Kiwamu Watanabe

IPC分类号： H04N11/04

CPC分类号： H04N19/423 ,  H04N19/44 ,  H04N19/61

摘要： A picture processing apparatus includes a decoder configured to decode encoded data to generate a decoded picture. A picture memory has a plurality of banks each containing a plurality of pages to which row addresses are assigned, and is configured to store the decoded picture. A bank selector is configured to divide the decoded picture into a plurality of blocks, and to select a page of a different bank as a write location for a block adjacent in at least one of either a horizontal direction or a vertical direction. A write controller is configured to write pixel data of pixels occupying even lines of each of the blocks, and pixel data of pixels occupying odd lines of each of the blocks in a column address direction of each of the page in an alternating manner.

摘要翻译： 图像处理装置包括：解码器，被配置为对编码数据进行解码以生成解码图像。 图像存储器具有多个存储体，每个存储体包含分配了行地址的多个页面，并且被配置为存储解码图像。 存储体选择器被配置为将解码图像划分为多个块，并且选择不同存储体的页作为在水平方向或垂直方向中的至少一个中相邻的块的写入位置。 写入控制器被配置为写入占据每个块的偶数行的像素的像素数据，并且以交替的方式在每个页面的列地址方向上占据每个块的奇数行的像素的像素数据。

公开(公告)号：US07447830B2

公开(公告)日：2008-11-04

申请号：US11365533

申请日：2006-03-02

申请人： Kunihiko Yahagi

发明人： Kunihiko Yahagi

IPC分类号： G06F12/00

CPC分类号： G06F13/1673

摘要： An information processing system includes a plurality of memories grouped into a first memory group and a second memory group, a data processor transmitting a data access request to the memories, and a memory controller controlling data transfer between the data processor and the plurality of memories. The memory controller includes an address calculation circuit calculating a second data address from a first data address included in the data access request, and a control unit controlling operation of the first and the second memory group by transmitting a first and a second control command in different clock cycles.

摘要翻译： 信息处理系统包括分组为第一存储器组和第二存储器组的多个存储器，向存储器发送数据访问请求的数据处理器，以及控制数据处理器与多个存储器之间的数据传送的存储器控​​制器。 存储器控制器包括：地址计算电路，从包含在数据访问请求中的第一数据地址计算第二数据地址;以及控制单元，通过发送不同的第一和第二控制命令来控制第一和第二存储器组的操作 时钟周期。

公开(公告)号：US06584155B2

公开(公告)日：2003-06-24

申请号：US09746020

申请日：2000-12-26

申请人： Hideki Takeda ,  Kunihiko Yahagi

发明人： Hideki Takeda ,  Kunihiko Yahagi

IPC分类号： H04N712

CPC分类号： H04N5/145 ,  G06T7/238 ,  G06T2207/10016 ,  H04N19/533 ,  H04N19/56 ,  H04N19/57

摘要： The correlation between a coded block on the screen of the current image and a plurality of candidate blocks which exist in a search area on a reference screen temporally different from the current image and which has the same area as that of the coded block is obtained to select a candidate block having the highest correlation to obtain its displacement as a primary motion vector. Then, the positional relationship between a motion vector/corresponding candidate block and the reference screen is estimated to determine whether the search area/candidate block is positioned inside of the boundary of the reference screen. When a part of the search area/candidate block is positioned outside of the boundary, the position of the primary motion vector so that the search area/candidate block is located inside of the boundary of the reference. Thereafter, a secondary motion vector is estimated using the corrected motion vector and the correction quantity to obtain a desired motion vector on the basis of the primary motion vector, the correction quantity and the secondary motion vector. Thus, the correction quantity is added during the motion vector estimation for the edge of the reference screen, to put the search area in the reference screen during the estimation of a desired motion vector, so as to improve the estimation precision.

摘要翻译： 获得当前图像的屏幕上的编码块与存在于与当前图像暂时不同的参考画面上的搜索区域中的与编码块的区域相同的区域中的编码块之间的相关性 选择具有最高相关性的候选块以获得其位移作为主要运动矢量。 然后，估计运动矢量/相应的候选块与参考屏幕之间的位置关系，以确定搜索区域/候选块是否位于参考屏幕的边界内。 当搜索区域/候选块的一部分位于边界之外时，主运动矢量的位置使得搜索区域/候选块位于参考的边界的内侧。 此后，使用校正的运动矢量和校正量来估计二次运动矢量，以基于主运动矢量，校正量和次要运动矢量来获得期望的运动矢量。 因此，在参考屏幕的边缘的运动矢量估计期间添加校正量，以在估计期望运动矢量期间将搜索区域放入参考屏幕中，以便提高估计精度。

公开(公告)号：US20070033319A1

公开(公告)日：2007-02-08

申请号：US11365533

申请日：2006-03-02

申请人： Kunihiko Yahagi

发明人： Kunihiko Yahagi

IPC分类号： G06F12/06 ,  G06F13/00

CPC分类号： G06F13/1673

摘要： An information processing system includes a plurality of memories grouped into a first memory group and a second memory group, a data processor transmitting a data access request to the memories, and a memory controller controlling data transfer between the data processor and the plurality of memories. The memory controller includes an address calculation circuit calculating a second data address from a first data address included in the data access request, and a control unit controlling operation of the first and the second memory group by transmitting a first and a second control command in different clock cycles.

摘要翻译： 信息处理系统包括分组为第一存储器组和第二存储器组的多个存储器，向存储器发送数据访问请求的数据处理器，以及控制数据处理器与多个存储器之间的数据传送的存储器控​​制器。 存储器控制器包括：地址计算电路，从包含在数据访问请求中的第一数据地址计算第二数据地址;以及控制单元，通过发送不同的第一和第二控制命令来控制第一和第二存储器组的操作 时钟周期。

公开(公告)号：US07124263B2

公开(公告)日：2006-10-17

申请号：US10717570

申请日：2003-11-21

申请人： Kunihiko Yahagi

发明人： Kunihiko Yahagi

IPC分类号： G06F12/00 ,  G06F1/12 ,  G06F1/04 ,  G06K5/04

CPC分类号： G06F13/1647

摘要： A memory controller includes a state generator configured to generate a plurality of state information signals in response to command requests associated with a plurality of banks in a memory. An enable signal generator is configured to generate a plurality of enable signals indicating whether the state information signals are valid or invalid. A bank controller is configured to generate a command based on the state information signals and the enable signals.

摘要翻译： 存储器控制器包括状态发生器，其被配置为响应于与存储器中的多个存储体相关联的命令请求而生成多个状态信息信号。 使能信号发生器被配置为产生指示状态信息信号是有效还是无效的多个使能信号。 银行控制器被配置为基于状态信息信号和使能信号产生命令。

公开(公告)号：US20050010718A1

公开(公告)日：2005-01-13

申请号：US10717570

申请日：2003-11-21

申请人： Kunihiko Yahagi

发明人： Kunihiko Yahagi

IPC分类号： G06F12/06 ,  G06F12/00 ,  G06F13/16

CPC分类号： G06F13/1647

摘要： A memory controller includes a state generator configured to generate a plurality of state information signals in response to command requests associated with a plurality of banks in a memory. An enable signal generator is configured to generate a plurality of enable signals indicating whether the state information signals are valid or invalid. A bank controller is configured to generate a command based on the state information signals and the enable signals.

摘要翻译： 存储器控制器包括状态发生器，其被配置为响应于与存储器中的多个存储体相关联的命令请求而生成多个状态信息信号。 使能信号发生器被配置为产生指示状态信息信号是有效还是无效的多个使能信号。 银行控制器被配置为基于状态信息信号和使能信号产生命令。