公开(公告)号：US07127717B2

公开(公告)日：2006-10-24

申请号：US10216846

申请日：2002-08-13

申请人： Tatsuya Kawashimo ,  Yoshio Miki ,  Hiroaki Fujii ,  Akihiro Takamura

发明人： Tatsuya Kawashimo ,  Yoshio Miki ,  Hiroaki Fujii ,  Akihiro Takamura

IPC分类号： G06F9/46 ,  G06F11/00 ,  G06F15/173

CPC分类号： H04L67/1008 ,  H04L29/06 ,  H04L67/1002 ,  H04L67/1029 ,  H04L69/329 ,  H04L2029/06054

摘要： A hierarchical server system efficiently balances the processing load thereon and for shortening the processing time therein is provided, such as a web server system. A system controller, a load balancing device, and a shared memory are provided in a multi-layer server system made of a plurality of servers. When processing implemented with a first layer server is temporarily stopped in order to acquire information needed for processing from a second layer server, process information needed to resume the processing is recorded in the shared memory. When the necessary information is sent back to the first layer server, the system controller inquires about work statuses of all first layer servers to select another first layer server to resume the processing based upon the inquiry results. The then selected first layer server then resumes the processing using the information that was sent back and the process information in the shared memory.

摘要翻译： 分层服务器系统有效平衡其上的处理负担，并且缩短了其中的处理时间，诸如web服务器系统。 在由多个服务器构成的多层服务器系统中提供系统控制器，负载平衡装置和共享存储器。 当为了从第二层服务器获取处理所需的信息时，当暂时停止用第一层服务器实施的处理时，恢复处理所需的处理信息被记录在共享存储器中。 当必要的信息被发送回第一层服务器时，系统控制器询问所有第一层服务器的工作状态，以选择另一个第一层服务器，以根据查询结果恢复处理。 然后，所选择的第一层服务器使用发回的信息和共享存储器中的处理信息来恢复处理。

公开(公告)号：US06832298B2

公开(公告)日：2004-12-14

申请号：US10229053

申请日：2002-08-28

申请人： Hiroaki Fujii ,  Yoshio Miki ,  Tatsuya Kawashimo ,  Akihiro Takamura

发明人： Hiroaki Fujii ,  Yoshio Miki ,  Tatsuya Kawashimo ,  Akihiro Takamura

IPC分类号： G06F1200

CPC分类号： G06F11/203 ,  G06F11/2038 ,  G06F11/2041 ,  G06F11/2043 ,  G06F11/2046 ,  G06F11/2051

摘要： A main logical unit and a standby logical unit are defined by a process controller in a shared main memory multiprocessor, and an information storage space accessible from both logical units is provided. The main logical unit stores address information onto that information storage space by indicating a memory area it controls as the main memory area. When failover or cloning becomes necessary, the standby logical unit searches the information on the applicable address. Then from the applicable information, it also searches information on the main memory area controlled by the main logical unit to establish in itself and forms a processing environment and state identical to the main logical unit such that the standby logical unit takes over all or a portion of the processing of the main logical unit. This enables the construction of a server system of high operability to overcome failures and poor response times by failover and cloning, etc.

摘要翻译： 主逻辑单元和备用逻辑单元由共享主存储器多处理器中的过程控制器定义，并且提供从两个逻辑单元可访问的信息存储空间。 主逻辑单元通过指示其控制的存储区域作为主存储区域将地址信息存储到该信息存储空间。 当需要故障转移或克隆时，备用逻辑单元将搜索适用地址的信息。 然后，从适用的信息中，还搜索由主逻辑单元控制的主存储区域的信息，以自己建立并形成与主逻辑单元相同的处理环境和状态，使得备用逻辑单元接管所有或部分 的主要逻辑单元的处理。 这使得能够构建高可操作性的服务器系统，以通过故障切换和克隆等来克服故障和差的响应时间。

公开(公告)号：US20050160407A1

公开(公告)日：2005-07-21

申请号：US10933218

申请日：2004-09-03

申请人： Akihiro Takamura ,  Yoshio Miki

发明人： Akihiro Takamura ,  Yoshio Miki

IPC分类号： G06F12/08 ,  G06F9/30 ,  G06F9/38 ,  G06F9/44 ,  G06F9/455

CPC分类号： G06F9/455

摘要： For reducing instruction cache misses in emulation by a dynamic conversion method, it is judged whether or not instruction cache conflict with a portion of an emulation program, whose execution frequency is high, occurs in an emulation operation, and only addresses not bringing about cache conflict are set as converted instruction storing areas. Thereby, instruction cache misses in a dynamic conversion type emulator are reduced, and the emulation speed is improved.

摘要翻译： 为了通过动态转换方法减少仿真中的指令高速缓存未命中，判断在仿真操作中是否发生指令高速缓冲存储器与执行频率高的仿真程序的一部分冲突，并且仅存在不引起缓存冲突的地址 被设置为转换指令存储区域。 因此，动态转换型仿真器中的指令高速缓存未命中被减少，仿真速度提高。

公开(公告)号：US07617087B2

公开(公告)日：2009-11-10

申请号：US10933218

申请日：2004-09-03

申请人： Akihiro Takamura ,  Yoshio Miki

发明人： Akihiro Takamura ,  Yoshio Miki

IPC分类号： G06F9/455 ,  G06G9/45

CPC分类号： G06F9/455

摘要： A construction of the present invention includes a procedure of setting in advance a storing area in a converted instruction storing area table for recording a corresponding relation between a program before conversion and a storing address of a converted program at an initialization processing portion of an emulation program. In setting the storing area, address information on a memory on a portion whose execution frequency is high upon an emulation operation is acquired, and an address that brings about cache conflict on an instruction cache with the portion whose execution frequency is high is excepted and set as an area to store therein a converted instruction.

摘要翻译： 本发明的结构包括在转换指令存储区表中预先设定存储区的步骤，用于在仿真程序的初始化处理部分记录转换前的程序与转换程序的存储地址之间的对应关系 。 在设置存储区域时，获取在仿真操作时执行频率高的部分上的存储器上的地址信息，并且对具有执行频率高的部分的指令高速缓冲存储器进行高速缓存冲突的地址被异常和设置 作为在其中存储转换指令的区域。

公开(公告)号：US08966166B2

公开(公告)日：2015-02-24

申请号：US13468370

申请日：2012-05-10

申请人： Yoshio Nishioka ,  Akihiro Takamura

发明人： Yoshio Nishioka ,  Akihiro Takamura

IPC分类号： G06F12/00 ,  G06F13/16

CPC分类号： G06F13/16 ,  G06F13/161

摘要： There is provided with an information processing apparatus comprising a DRAM, a memory controller configured to access the DRAM, and a bus master configured to send, to the memory controller, an access request to the DRAM, the bus master comprises a transmission unit configured to transmit, to the memory controller, using a signal indicating a type of burst access which is requested of the memory controller by the bus master, an instruction to designate that an auto-precharge operation is not to be performed after accessing the first address, and an instruction to designate that an auto-precharge operation is to be performed after accessing the first address.

摘要翻译： 提供了一种信息处理装置，包括DRAM，被配置为访问DRAM的存储器控​​制器和被配置为向存储器控制器发送对DRAM的访问请求的总线主机，总线主机包括：传输单元，被配置为 使用指示由总线主机请求存储器控制器的脉冲串访问类型的信号发送到存储器控制器，指定在访问第一地址之后不执行自动预充电操作;以及 指定在访问第一地址之后执行自动预充电操作。

公开(公告)号：US20120317351A1

公开(公告)日：2012-12-13

申请号：US13468370

申请日：2012-05-10

申请人： Yoshio Nishioka ,  Akihiro Takamura

发明人： Yoshio Nishioka ,  Akihiro Takamura

IPC分类号： G06F12/00

CPC分类号： G06F13/16 ,  G06F13/161

摘要： There is provided with an information processing apparatus comprising a DRAM, a memory controller configured to access the DRAM, and a bus master configured to send, to the memory controller, an access request to the DRAM, the bus master comprises a transmission unit configured to transmit, to the memory controller, using a signal indicating a type of burst access which is requested of the memory controller by the bus master, an instruction to designate that an auto-precharge operation is not to be performed after accessing the first address, and an instruction to designate that an auto-precharge operation is to be performed after accessing the first address.

摘要翻译： 提供了一种信息处理装置，包括DRAM，被配置为访问DRAM的存储器控​​制器和被配置为向存储器控制器发送对DRAM的访问请求的总线主机，总线主机包括：传输单元，被配置为 使用指示由总线主机请求存储器控制器的脉冲串访问类型的信号发送到存储器控制器，指定在访问第一地址之后不执行自动预充电操作;以及 指定在访问第一地址之后执行自动预充电操作。

公开(公告)号：US09019304B2

公开(公告)日：2015-04-28

申请号：US12935963

申请日：2009-05-29

申请人： Shinya Takeichi ,  Waki Murakami ,  Satoru Mamiya ,  Jun Fujisawa ,  Shuichi Okamura ,  Atsushi Date ,  Takeshi Suzuki ,  Akihiro Takamura ,  Toru Nomakuchi ,  Shigeru Sakamoto

发明人： Shinya Takeichi ,  Waki Murakami ,  Satoru Mamiya ,  Jun Fujisawa ,  Shuichi Okamura ,  Atsushi Date ,  Takeshi Suzuki ,  Akihiro Takamura ,  Toru Nomakuchi ,  Shigeru Sakamoto

IPC分类号： G09G5/00 ,  G09G5/36 ,  G06T11/00 ,  G09G5/14

CPC分类号： G09G5/363 ,  G06T11/00 ,  G09G5/006 ,  G09G5/14 ,  G09G2340/0414 ,  G09G2340/0421 ,  G09G2340/0471 ,  G09G2340/0478 ,  G09G2340/125

摘要： According to an image processing apparatus and a control method thereof of the present invention, a graphics drawing result is obtained in accordance with one or more graphics drawing commands included in drawing commands, a clipping command is generated from one or more moving image drawing commands included in the drawing commands, and clipped graphics is obtained by clipping the graphics drawing result using the clipping command. Further, moving image data processed in accordance with the one or more moving image drawing commands included in the drawing commands is generated, and the generated moving image data and the clipped graphics are composed and output.

摘要翻译： 根据本发明的图像处理装置及其控制方法，根据绘制命令中包括的一个或多个图形绘制命令获得图形绘制结果，从包括的一个或多个运动图像绘制命令生成裁剪命令 在绘图命令中，通过使用裁剪命令剪切图形绘制结果来获得剪切图形。 此外，生成根据包括在绘制命令中的一个或多个运动图像绘制命令处理的运动图像数据，并且生成的运动图像数据和剪切图形被组合和输出。

公开(公告)号：US08451191B2

公开(公告)日：2013-05-28

申请号：US12502047

申请日：2009-07-13

申请人： Masayuki Odagawa ,  Akihiro Takamura ,  Tetsurou Kitashou

发明人： Masayuki Odagawa ,  Akihiro Takamura ,  Tetsurou Kitashou

IPC分类号： G09G5/00

CPC分类号： G06F3/147 ,  G09G5/14

摘要： In a display system which includes a plurality of space management units which are hierarchically connected, and each of which manages a predetermined space region as a management space region, a content management unit which manages one or a plurality of contents, and a plurality of display units which display information on display regions. Wherein each of the plurality of display units displays a content arranged in a subspace corresponding to a self display region in the management space region.

摘要翻译： 在包括分层连接的多个空间管理单元和管理作为管理空间区域的预定空间区域的多个空间管理单元的显示系统中，管理一个或多个内容的内容管理单元和多个显示 在显示区域显示信息的单元。 其中，所述多个显示单元中的每一个显示在所述管理空间区域中对应于自身显示区域的子空间中排列的内容。

公开(公告)号：US20120328214A1

公开(公告)日：2012-12-27

申请号：US13490260

申请日：2012-06-06

申请人： Akihiro Takamura ,  Tetsurou Kitashou

发明人： Akihiro Takamura ,  Tetsurou Kitashou

IPC分类号： G06K9/32

CPC分类号： G06T5/001 ,  G06T3/0093 ,  H04N9/3185

摘要： This apparatus obtains a mapped position (xo, yo) of (xi, yi), acquires (xi′, yi′) by performing inverse mapping for each reference position being based on (xo, yo), obtains (xi″, yi″) by performing inverse mapping for integer parts xoc and yoc of xo and yo respectively, and performs interpolation using fraction parts of x- and y-coordinates of a position, of (xi″, yi″) and (xi′, yi′), whose integer parts of the x- and y-coordinates respectively coincide with xi and yi, and peripheral pixel values of (xi, yi).

摘要翻译： 该装置通过对基于（xo，yo）的每个参考位置执行逆映射来获得（xi，yi）的映射位置（xo，y i），获得（xi'，yi'），获得（xi'，yi' ）分别通过对xo和y的整数部分xoc和yoc执行逆映射，并使用（xi'，yi“）和（xi'，yi'）的位置的x和y坐标的分数部分进行插值， ，其x和y坐标的整数部分分别与xi和yi一致，以及（xi，yi）的周边像素值。

公开(公告)号：US20090310670A1

公开(公告)日：2009-12-17

申请号：US12484861

申请日：2009-06-15

申请人： Masayuki Odagawa ,  Wataru Ochiai ,  Akihiro Takamura

发明人： Masayuki Odagawa ,  Wataru Ochiai ,  Akihiro Takamura

IPC分类号： H04N7/12

CPC分类号： H04N7/24 ,  H04N19/176 ,  H04N19/187 ,  H04N19/188 ,  H04N19/196 ,  H04N19/44 ,  H04N19/70

摘要： An information processing system for performing processing of dividing a moving image into tiles and packetizing and outputting information corresponding to each tile includes a process time measuring packet generation unit adapted to generate and transmit a process time measuring packet in which a packet sending time is set to measure a packet process time, a packet process time measuring unit adapted to measure, based on the packet sending time set in the process time measuring packet and the reception time of the process time measuring packet, the packet process time necessary for processing a packet, a determination unit adapted to determine, based on the packet process time, the timestamp of the moving image divided into the tiles, and a packetization unit adapted to execute processing of packetizing and outputting the timestamp and the information of the moving image divided into the tiles.

摘要翻译： 一种用于执行将运动图像划分成瓦片并分组并输出与每个瓦片相对应的信息的处理的信息处理系统，包括：处理时间测量分组生成单元，适于生成并发送分组发送时间设置为 测量分组处理时间，分组处理时间测量单元，基于在处理时间测量分组中设置的分组发送时间和处理时间测量分组的接收时间来测量处理分组所需的分组处理时间， 确定单元，适于基于分组处理时间确定划分为瓦片的运动图像的时间戳;以及分组单元，适用于执行分组和输出时间戳的处理以及划分为瓦片的运动图像的信息 。