公开(公告)号：US5303344A

公开(公告)日：1994-04-12

申请号：US659705

申请日：1991-02-25

申请人： Tatsuya Yokoyama ,  Susumu Matsui ,  Matsuaki Terada ,  Tetsuhiko Hirata ,  Mika Mizutani

发明人： Tatsuya Yokoyama ,  Susumu Matsui ,  Matsuaki Terada ,  Tetsuhiko Hirata ,  Mika Mizutani

IPC分类号： H04L29/06 ,  G06F3/00 ,  G06F15/16

CPC分类号： H04L29/06 ,  H04L69/22

摘要： A communication control equipment connected between a computer and a network so as to perform protocol processing at a high speed, has a buffer memory connected between a computer interface circuit and a network interface circuit through a first path for data transfer, so as to temporarily store communication data, and a protocol processor connected between the computer interface circuit and the network interface circuit through a second path for control information transfer. The protocol processor is also connected to the buffer memory through a third path so as to effect protocol processing on the communication data within the buffer memory. The protocol processor includes a plurality of processor units connected in series in the second path so as to respond to control information received from the second path to make access to the buffer memory through the third path and to execute a first category of protocol processing necessary in normal data transfer on the communication data stored in the buffer memory. If protocol processing other than the first category of protocol processing on the communication data is necessary, the processor units supply the control information to the third path. The protocol processing also includes a second processor which operates as a backend processor for the processor units and which is connected to the third path so as to respond to the control information received from the third path to execute protocol processing other than the first category of protocol processing on the communication data stored in the buffer memory.

摘要翻译： 连接在计算机和网络之间以便以高速执行协议处理的通信控制设备通过用于数据传送的第一路径在计算机接口电路和网络接口电路之间连接有缓冲存储器，以便临时存储 通信数据和通过用于控制信息传送的第二路径连接在计算机接口电路和网络接口电路之间的协议处理器。 协议处理器还通过第三路径连接到缓冲存储器，以便对缓冲存储器内的通信数据进行协议处理。 协议处理器包括在第二路径中串联连接的多个处理器单元，以响应从第二路径接收到的控制信息，以通过第三路径访问缓冲存储器，并执行第一类协议处理 对存储在缓冲存储器中的通信数据进行正常数据传输。 如果需要除通信数据上的第一类协议处理之外的协议处理，则处理器单元将控制信息提供给第三路径。 协议处理还包括第二处理器，其作为用于处理器单元的后端处理器并且连接到第三路径，以响应从第三路径接收到的控制信息来执行不同于第一类协议的协议处理 对存储在缓冲存储器中的通信数据进行处理。

公开(公告)号：US5056058A

公开(公告)日：1991-10-08

申请号：US489243

申请日：1990-03-05

申请人： Tetsuhiko Hirata ,  Susumu Matsui ,  Matsuaki Terada ,  Tatsuya Yokoyama ,  Sinichi Kouyama

发明人： Tetsuhiko Hirata ,  Susumu Matsui ,  Matsuaki Terada ,  Tatsuya Yokoyama ,  Sinichi Kouyama

IPC分类号： G06F13/00 ,  G06F15/17 ,  H04L29/06 ,  H04L29/08

CPC分类号： H04L29/06 ,  G06F15/17 ,  H04L69/22

摘要： A protocol high-speed processing method to be used in a first communication control equipment for communications with a second communication equipment connected through a transmission line in accordance with a predetermined communication protocol. The communication control equipment predicts the type of communication frame to be received next from the communication line, in accordance with type of communication frame previously transmitted to or received from said transmission line, and prepares information necessary for a process of receiving said predicted communication frame and information of a part of the communication frame to be transmitted subsequent to the receiving process, to await the reception of a next communication frame. As a result, the receiving process time and the response process time can be reduced when the actually received communication frame is consistent with the predicted one.

摘要翻译： 一种协议高速处理方法，用于与根据预定通信协议通过传输线连接的第二通信设备进行通信的第一通信控制设备。 通信控制装置根据先前发送到或从所述传输线接收的通信帧的类型来预测下一次从通信线路接收的通信帧的类型，并且准备接收所述预测通信帧所需的信息和 在接收处理之后要发送的通信帧的一部分的信息，等待接收下一个通信帧。 结果，当实际接收到的通信帧与预测的通信帧一致时，可以减少接收处理时间和响应处理时间。

公开(公告)号：US5678060A

公开(公告)日：1997-10-14

申请号：US331106

申请日：1994-10-28

申请人： Tatsuya Yokoyama ,  Tetsuhiko Hirata ,  Mika Mizutani ,  Osamu Takada

发明人： Tatsuya Yokoyama ,  Tetsuhiko Hirata ,  Mika Mizutani ,  Osamu Takada

IPC分类号： G06F13/00 ,  H04L12/931 ,  H04L12/951 ,  H04L29/06 ,  G06F3/00 ,  G06F15/16 ,  G06F15/56

CPC分类号： H04L12/5601 ,  H04L2012/5615 ,  H04L2012/5616 ,  H04L2012/563 ,  H04L2012/5652

摘要： Communication control equipment for connecting a computer system to a network and supporting the computer system to set a plurality of connections on the network and perform parallel communication between computers. The communication control equipment includes an interface circuit for the computer system, a microprocessor for performing communication control processing, a local memory for storing programs and work data, a buffer memory for temporarily storing transmission and reception data, a DMA transfer unit for performing data transfer between a memory in the computer system and the buffer memory and protocol header transfer between the buffer memory and the local memory, a network controller for controlling transmission and reception of data to the network, and a header retrieval unit for predicting a protocol header of a frame to be next received in correspondence to each of a plurality of connections and retrieving a header corresponding to a protocol header of a received frame transferred by the DMA transfer unit.

摘要翻译： 用于将计算机系统连接到网络并支持计算机系统以在网络上设置多个连接并执行计算机之间的并行通信的通信控制设备。 通信控制设备包括用于计算机系统的接口电路，用于执行通信控制处理的微处理器，用于存储程序和工作数据的本地存储器，用于临时存储发送和接收数据的缓冲存储器，用于执行数据传输的DMA传送单元 在计算机系统中的存储器和缓冲存储器之间以及缓冲存储器和本地存储器之间的协议报头传送之间，用于控制数据到网络的传输和接收的网络控制器，以及用于预测 帧将被相应地接收到多个连接中的每一个并且检索对应于由DMA传送单元传送的接收帧的协议报头的报头。

公开(公告)号：US5623606A

公开(公告)日：1997-04-22

申请号：US968589

申请日：1992-10-29

申请人： Tatsuya Yokoyama ,  Tetsuhiko Hirata ,  Mika Mizutani

发明人： Tatsuya Yokoyama ,  Tetsuhiko Hirata ,  Mika Mizutani

IPC分类号： G06F13/00 ,  G06F13/38 ,  H04L12/801 ,  H04L12/875 ,  H04L12/911 ,  H04L13/08 ,  H04L29/08 ,  H04J3/14

CPC分类号： G06F13/387 ,  H04L49/90 ,  H04L49/9073

摘要： In a communication control equipment for transmitting data in an external predetermined memory to a network, there are provided a buffer memory unit for temporarily holding the data transferred thereto, a data transfer unit for performing a data transfer between the predetermined memory and the buffer memory unit, a unit for executing a protocol processing with regard to data held in the buffer memory unit, a control unit for controlling a transmission of the data processed by the protocol processing to the network, and a unit for producing a transmission start instruction at a start time instant within a range defined from a time instant when 1-packet data transfer from the predetermined memory to the buffer memory unit is commenced until a time instant when this data transfer is completed. The transmission start instruction is produced under a condition that the lower a data transfer speed from the predetermined memory to the buffer memory unit is relative to a transmission speed of the network, the later the start time instant is. A unit is also provided for causing the control unit to commence the transmission of the data processed by the protocol processing to the network at a later time instant during the time instant when the transmission start instruction is produced and the time instant when the protocol processing is terminated.

摘要翻译： 在用于将外部预定存储器中的数据发送到网络的通信控制设备中，提供了用于临时保存传送到其中的数据的缓冲存储器单元，用于在预定存储器和缓冲存储器单元之间执行数据传送的数据传送单元 ，用于执行关于保存在缓冲存储器单元中的数据的协议处理的单元，控制单元，用于控制通过协议处理对网络进行处理的数据的传输，以及用于在开始时产生传输开始指令的单元 在从预定存储器到缓冲存储器单元的1分组数据传输开始的时刻定义的范围内的时刻，直到完成该数据传输的时刻。 在从预定存储器到缓冲存储器单元的数据传输速度越低相对于网络传输速度越低的开始时刻之后就产生传输开始指令。 还提供了一个单元，用于使得控制单元在产生传输开始指令的时刻和在协议处理为的时刻的时间点开始将协议处理所处理的数据发送到网络 终止了

公开(公告)号：US5345410A

公开(公告)日：1994-09-06

申请号：US890712

申请日：1992-05-29

申请人： Tatsuya Yokoyama ,  Tetsuhiko Hirata

发明人： Tatsuya Yokoyama ,  Tetsuhiko Hirata

IPC分类号： G06F7/02 ,  G06F7/535 ,  G06F7/537 ,  G06F7/72 ,  G06F9/30 ,  G06F13/00 ,  G06F13/42 ,  H04L29/08

CPC分类号： G06F7/72

摘要： An arithmetic-logic unit ALU having three data input ports A, B and C, a modulo adder/subtracter for executing an arithmetic-logic operation of (A.+-.B) mod (C+1), a comparator for determining whether the input data A, B and C satisfy at least one of the relationship of A.ltoreq.B.ltoreq., A.ltoreq.B

摘要翻译： 具有三个数据输入端口A，B和C的算术逻辑单元ALU，用于执行（A +/- B）mod（C + 1）的算术运算的模加法器/减法器，用于确定输入 数据A，B和C从模运算视点满足A A和A