公开(公告)号：US5056058A

公开(公告)日：1991-10-08

申请号：US489243

申请日：1990-03-05

申请人： Tetsuhiko Hirata ,  Susumu Matsui ,  Matsuaki Terada ,  Tatsuya Yokoyama ,  Sinichi Kouyama

发明人： Tetsuhiko Hirata ,  Susumu Matsui ,  Matsuaki Terada ,  Tatsuya Yokoyama ,  Sinichi Kouyama

IPC分类号： G06F13/00 ,  G06F15/17 ,  H04L29/06 ,  H04L29/08

CPC分类号： H04L29/06 ,  G06F15/17 ,  H04L69/22

摘要： A protocol high-speed processing method to be used in a first communication control equipment for communications with a second communication equipment connected through a transmission line in accordance with a predetermined communication protocol. The communication control equipment predicts the type of communication frame to be received next from the communication line, in accordance with type of communication frame previously transmitted to or received from said transmission line, and prepares information necessary for a process of receiving said predicted communication frame and information of a part of the communication frame to be transmitted subsequent to the receiving process, to await the reception of a next communication frame. As a result, the receiving process time and the response process time can be reduced when the actually received communication frame is consistent with the predicted one.

摘要翻译： 一种协议高速处理方法，用于与根据预定通信协议通过传输线连接的第二通信设备进行通信的第一通信控制设备。 通信控制装置根据先前发送到或从所述传输线接收的通信帧的类型来预测下一次从通信线路接收的通信帧的类型，并且准备接收所述预测通信帧所需的信息和 在接收处理之后要发送的通信帧的一部分的信息，等待接收下一个通信帧。 结果，当实际接收到的通信帧与预测的通信帧一致时，可以减少接收处理时间和响应处理时间。

公开(公告)号：US5303344A

公开(公告)日：1994-04-12

申请号：US659705

申请日：1991-02-25

申请人： Tatsuya Yokoyama ,  Susumu Matsui ,  Matsuaki Terada ,  Tetsuhiko Hirata ,  Mika Mizutani

发明人： Tatsuya Yokoyama ,  Susumu Matsui ,  Matsuaki Terada ,  Tetsuhiko Hirata ,  Mika Mizutani

IPC分类号： H04L29/06 ,  G06F3/00 ,  G06F15/16

CPC分类号： H04L29/06 ,  H04L69/22

摘要： A communication control equipment connected between a computer and a network so as to perform protocol processing at a high speed, has a buffer memory connected between a computer interface circuit and a network interface circuit through a first path for data transfer, so as to temporarily store communication data, and a protocol processor connected between the computer interface circuit and the network interface circuit through a second path for control information transfer. The protocol processor is also connected to the buffer memory through a third path so as to effect protocol processing on the communication data within the buffer memory. The protocol processor includes a plurality of processor units connected in series in the second path so as to respond to control information received from the second path to make access to the buffer memory through the third path and to execute a first category of protocol processing necessary in normal data transfer on the communication data stored in the buffer memory. If protocol processing other than the first category of protocol processing on the communication data is necessary, the processor units supply the control information to the third path. The protocol processing also includes a second processor which operates as a backend processor for the processor units and which is connected to the third path so as to respond to the control information received from the third path to execute protocol processing other than the first category of protocol processing on the communication data stored in the buffer memory.

摘要翻译： 连接在计算机和网络之间以便以高速执行协议处理的通信控制设备通过用于数据传送的第一路径在计算机接口电路和网络接口电路之间连接有缓冲存储器，以便临时存储 通信数据和通过用于控制信息传送的第二路径连接在计算机接口电路和网络接口电路之间的协议处理器。 协议处理器还通过第三路径连接到缓冲存储器，以便对缓冲存储器内的通信数据进行协议处理。 协议处理器包括在第二路径中串联连接的多个处理器单元，以响应从第二路径接收到的控制信息，以通过第三路径访问缓冲存储器，并执行第一类协议处理 对存储在缓冲存储器中的通信数据进行正常数据传输。 如果需要除通信数据上的第一类协议处理之外的协议处理，则处理器单元将控制信息提供给第三路径。 协议处理还包括第二处理器，其作为用于处理器单元的后端处理器并且连接到第三路径，以响应从第三路径接收到的控制信息来执行不同于第一类协议的协议处理 对存储在缓冲存储器中的通信数据进行处理。

公开(公告)号：US5150365A

公开(公告)日：1992-09-22

申请号：US548431

申请日：1990-07-05

申请人： Tetsuhiko Hirata ,  Kazuo Yagyu ,  Matsuaki Terada ,  Hiroshi Nakase ,  Shigeru Oshima ,  Motoyoshi Morito ,  Takahiko Nishizawa

发明人： Tetsuhiko Hirata ,  Kazuo Yagyu ,  Matsuaki Terada ,  Hiroshi Nakase ,  Shigeru Oshima ,  Motoyoshi Morito ,  Takahiko Nishizawa

IPC分类号： H04J1/04 ,  H04L12/28 ,  H04N7/10 ,  H04N7/54

CPC分类号： H04N7/10 ,  H04J1/045 ,  H04L12/2801 ,  H04N7/54

摘要： A base-band and broad-band coexisting communication system comprises a transmission path, a plurality of first data terminal units outputting data to be transmitted in the form of pulse signals (base band signals), a plurality of second data terminal units for outputting data to be transmitted in the form of modulated signals (broad band signals) each having a center frequency within a predetermined frequency range, and a plurality of low-pass filters, each connected to each of the first data transmission units, for cutting off high frequency components of the base band signal outputted by the first data terminal device at a predetermined cut-off frequency which does not overlap with the broad band signals.

摘要翻译： 基带和宽带共存通信系统包括传输路径，以脉冲信号（基带信号）的形式输出要发送的数据的多个第一数据终端单元，用于输出数据的多个第二数据终端单元 以每个具有预定频率范围内的中心频率的调制信号（宽带信号）的形式发送，以及多个低通滤波器，每个低通滤波器连接到每个第一数据传输单元，用于切断高频 以与宽带信号不重叠的预定截止频率由第一数据终端装置输出的基带信号的分量。

公开(公告)号：US4881167A

公开(公告)日：1989-11-14

申请号：US318439

申请日：1989-03-02

申请人： Hisao Sasaki ,  Matsuaki Terada ,  Susumu Matsui ,  Kenji Kawakita ,  Jiro Kashio ,  Shiro Baba ,  Yasushi Akao ,  Toshio Okochi

发明人： Hisao Sasaki ,  Matsuaki Terada ,  Susumu Matsui ,  Kenji Kawakita ,  Jiro Kashio ,  Shiro Baba ,  Yasushi Akao ,  Toshio Okochi

IPC分类号： G06F3/06 ,  G06F5/06 ,  G06F12/02 ,  G06F12/04 ,  G06F12/06

CPC分类号： H04L49/901 ,  G06F12/06 ,  G06F5/06 ,  H04L49/90 ,  H04L49/9021 ,  G06F2205/064

摘要： A data memory system includes a plurality of buffer regions each having a constant size so that serial data may be stored by linking the buffer regions. A descripter provided to correspond to each of the buffer regions includes memory region addressing information indicating the head address of the corresponding buffer region, data delimiting information indicating whether or not the data to be stored is terminated in the corresponding buffer region, and chain information indicating the head address of a next subsequent descripter.

摘要翻译： 数据存储系统包括多个缓冲区，每个缓冲区具有恒定的大小，从而通过链接缓冲区可以存储串行数据。 提供用于对应于每个缓冲区的描述符包括指示相应缓冲区的头地址的存储器区域寻址信息，指示要存储的数据是否终止在相应的缓冲区中的数据定界信息，以及指示 下一个下一个描述符的头地址。

公开(公告)号：US4941084A

公开(公告)日：1990-07-10

申请号：US201290

申请日：1988-05-27

申请人： Matsuaki Terada ,  Hiroshi Wataya ,  Satoru Takagi ,  Masao Sueki

发明人： Matsuaki Terada ,  Hiroshi Wataya ,  Satoru Takagi ,  Masao Sueki

IPC分类号： H04L29/02 ,  G06F9/445 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  H04L29/06

CPC分类号： H04L29/06 ,  G06F15/17337

摘要： A resource management system and method in a distributed processing system in which a plurality of computers are interconnected through a transmission line. A computer makes, upon accessing to a resource of another computer, inquiries about "Whether the intended resource exists" and "Ordering that if the intended resource exists, the interrogated computer should return a response indicative of attribute information of that resource" by using a so-called broadcasting function to simultaneously apprize all the computers constituting the distributed processing system of the same message.

摘要翻译： 一种分布式处理系统中的资源管理系统和方法，其中多个计算机通过传输线互连。 计算机在访问另一台计算机的资源时会查询有关“是否存在预期资源”和“如果预期资源存在命令，则询问的计算机应该返回指示该资源的属性信息的响应”，方法是使用 所谓的广播功能，以同时使构成同一消息的分布式处理系统的所有计算机。

公开(公告)号：US4447871A

公开(公告)日：1984-05-08

申请号：US230805

申请日：1981-02-02

申请人： Matsuaki Terada ,  Koji Yokota

发明人： Matsuaki Terada ,  Koji Yokota

IPC分类号： G06F13/12 ,  G06F13/42 ,  G06F15/16 ,  G06F9/19

CPC分类号： G06F13/128 ,  G06F13/4213

摘要： A data communication system which includes a data distributor, a communication station and a plurality of front-end-processors. These front-end-processors are connected with a computer through a common bus. The distributor distributes the data received by the station to one available front-end-processor, which preprocesses the received data, and transfers the pre-processed data to the computer through the bus. By operating the front-end-processors in parallel with respect to successively received packets of data, the processing speed of the system is increased.

摘要翻译： 一种包括数据分配器，通信站和多个前端处理器的数据通信系统。 这些前端处理器通过公共总线与计算机连接。 分配器将站接收的数据分配给一个可用的前端处理器，该前端处理器对接收的数据进行预处理，并通过总线将预处理的数据传送到计算机。 通过相对于连续接收的数据包并行操作前端处理器，系统的处理速度增加。

公开(公告)号：US5247518A

公开(公告)日：1993-09-21

申请号：US819821

申请日：1992-01-13

申请人： Yoshihiro Takiyasu ,  Toshiki Tanaka ,  Taihei Suzuki ,  Eiichi Amada ,  Yukiji Yamauchi ,  Mitsuhiro Yamaga ,  Matsuaki Terada ,  Kunio Hiyama

发明人： Yoshihiro Takiyasu ,  Toshiki Tanaka ,  Taihei Suzuki ,  Eiichi Amada ,  Yukiji Yamauchi ,  Mitsuhiro Yamaga ,  Matsuaki Terada ,  Kunio Hiyama

IPC分类号： H04J3/08 ,  H04J3/16 ,  H04L12/43 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04Q11/0478 ,  H04J3/08 ,  H04J3/1617 ,  H04L12/43 ,  H04J2203/0042 ,  H04J2203/0089 ,  H04L2012/5652 ,  H04L2012/5672

摘要： A high-speed ring LAN capable of accommodating at least one public network having a signal transmission rate of 155.57 MHz, and at least one sub-LAN having a signal transmission rate of 100 MHz. The high-speed LAN has a signal transmission rate of 155.52 Mbps .times.n (n is an even number). SONET (Synchronous Optical NETwork) subframes each comprising a 9 bytes .times.9 section overhead area and a 261 bytes .times.9 virtual container 4 (VC-4) area flow in a time-divisional n-multiplexed format. The respective node devices inserted in the transmission path have one or more ports to accommodate sub-LANs or public networks. Information is exchanged in units of a fixed-length packet between a received SONET subframe and an asynchronous port whereas information is exchanged in units of a byte between the SONET subframe and a synchronous port.

摘要翻译： 能够容纳具有155.57MHz的信号传输速率的至少一个公共网络的高速环形LAN以及信号传输速率为100MHz的至少一个子LAN。 高速LAN的信号传输速率为155.52Mbps xn（n为偶数）。 SONET（同步光网络）子帧，每个子帧包括时分多路复用格式的9字节×9部分开销区域和261字节×9虚拟容器4（VC-4）区域流。 插入传输路径中的各个节点设备具有一个或多个端口以适应子LAN或公共网络。 信息以接收的SONET子帧和异步端口之间的固定长度分组为单位进行交换，而以SONET子帧和同步端口之间的字节为单位交换信息。

公开(公告)号：US5103447A

公开(公告)日：1992-04-07

申请号：US399901

申请日：1989-08-29

申请人： Yoshihiro Takiyasu ,  Toshiki Tanaka ,  Taihei Suzuki ,  Eiichi Amada ,  Yukiji Yamauchi ,  Mitsuhiro Yamaga ,  Matsuaki Terada ,  Kunio Hiyama

发明人： Yoshihiro Takiyasu ,  Toshiki Tanaka ,  Taihei Suzuki ,  Eiichi Amada ,  Yukiji Yamauchi ,  Mitsuhiro Yamaga ,  Matsuaki Terada ,  Kunio Hiyama

IPC分类号： H04J3/08 ,  H04J3/16 ,  H04L12/43 ,  H04L12/56 ,  H04Q11/04

CPC分类号： H04J3/08 ,  H04J3/1617 ,  H04L12/43 ,  H04Q11/0478 ,  H04J2203/0042 ,  H04J2203/0089 ,  H04L2012/5652 ,  H04L2012/5672

摘要： A high-speed ring LAN capable of accommodating at least one public network having a signal transmission rate of 155.57 MHz, and at least one sub-LAN having a signal transmission rate of 100 MHz. The high-speed LAN has a signal transmission rate of 155.52 Mbps.times.n (n is an even number). SONET (Synchronous Optical NETwork) subframes each comprising a 9 bytes.times.9 section overhead area and a 261 bytes.times.9 virtual container 4 (VC-4) area flow in a time-divisional n-multiplexed format. The respective node devices inserted in the transmission path have one or more ports to accommodate sub-LANs or public networks. Information is exchanged in units of a fixed-length packet between a received SONET subframe and an asynchronous packet whereas information is exchanged in units of a byte between the SONET subframe and a synchronous port.

摘要翻译： 能够容纳具有155.57MHz的信号传输速率的至少一个公共网络的高速环形LAN以及信号传输速率为100MHz的至少一个子LAN。 高速LAN的信号传输速率为155.52Mbps×n（n为偶数）。 SONET（同步光网络）子帧，每个子帧包括时分多路复用格式的9字节×9部分开销区域和261字节×9虚拟容器4（VC-4）区域流。 插入传输路径中的各个节点设备具有一个或多个端口以适应子LAN或公共网络。 在接收的SONET子帧和异步分组之间以固定长度的分组为单位交换信息，而以SONET子帧和同步端口之间的字节为单位交换信息。

公开(公告)号：US5018133A

公开(公告)日：1991-05-21

申请号：US582781

申请日：1990-09-06

申请人： Masato Tsukakoshi ,  Yasuhiro Takahashi ,  Matsuaki Terada ,  Nobuyuki Takagishi

发明人： Masato Tsukakoshi ,  Yasuhiro Takahashi ,  Matsuaki Terada ,  Nobuyuki Takagishi

IPC分类号： H04L12/46 ,  H04L12/715 ,  H04L12/753 ,  H04L29/12

CPC分类号： H04L29/12254 ,  H04L12/462 ,  H04L29/12839 ,  H04L45/04 ,  H04L45/48 ,  H04L61/2038 ,  H04L61/6022

摘要： In a network system according to the hierarchical routing method, in which at least one main LAN and a plurality of sub-LANs are connected hierarchically through bridges, bridge IDs having the smallest values in the network are given to a plurality of bridges (first bridges) connected to the main LAN. Bridge IDs unique to each other having values greater than the bridge IDs of the first bridges are given to a plurality of bridges (second bridges) connecting sub-LANs. Each of the first bridges transmits periodically a control message (Hello message) for making the network in a tree structure by using some of the second bridges as backup bridges to the side of the sub-LANs. When a change takes place in the topology of the network, the reconstruction of the tree structure is effected in a localized part of the network including a position of hindrance, the root of the network being constituted by a particular first bridge.

摘要翻译： 在根据分层路由方法的网络系统中，其中至少一个主LAN和多个子LAN通过网桥分层连接，网络中具有最小值的网桥ID被提供给多个网桥（第一网桥 ）连接到主局域网。 将具有大于第一桥的桥ID的值彼此唯一的桥ID提供给连接子LAN的多个网桥（第二桥）。 每个第一桥接器周期性地发送控制消息（Hello消息），用于通过使用一些第二网桥作为子LAN侧面的备用网桥来使网络成树结构。 当在网络的拓扑中发生变化时，树结构的重构在网络的局部部分中实现，包括阻碍位置，网络的根由特定的第一桥构成。

公开(公告)号：US5247620A

公开(公告)日：1993-09-21

申请号：US554872

申请日：1990-07-20

申请人： Junji Fukuzawa ,  Akira Watanabe ,  Matsuaki Terada ,  Sadao Mizokawa

发明人： Junji Fukuzawa ,  Akira Watanabe ,  Matsuaki Terada ,  Sadao Mizokawa

IPC分类号： H04L12/46

CPC分类号： H04L12/4625 ,  H04L45/745 ,  H04L45/7453

摘要： A bridge apparatus for interconnecting networks in which at least two networks including a plurality of stations are connected, and which, when a transmission frame including an identifier of one station and an identifier of another station of a destination is received from the one station, forwards the transmission frame to a network to which the another station belongs based on the identifier of another station. A processor of the bridge apparatus for interconnecting networks performs delivery control of the transmission frame using an information which has been read out of an address check circuit for identifying the network to which the another station belongs with the identifier of the another station which is included in the transmission frame. The address check circuit comprises at least one hash memory in which hash computation results of respective addresses have been stored at respective address positions, and an address memory for storing a plurality of address informations showing a corresponding relationship between identifiers of respective stations and identifiers of respective networks at respective address positions.

摘要翻译： 一种用于互连网络的桥接装置，其中连接包括多个站的至少两个网络，并且当从一个站接收到包括一个站的标识符和目的地的另一站的标识符的传输帧时， 基于另一站的标识符将传输帧传送到另一站所属的网络。 用于互联网络的桥接装置的处理器使用从地址检查电路中读出的信息来执行传输帧的传送控制，该信息用于识别另一个站所属的网络与包含在其中的另一个站点的标识符 传输帧。 地址检查电路包括至少一个散列存储器，其中相应地址的散列计算结果已被存储在相应的地址位置，以及地址存储器，用于存储多个地址信息，该地址信息表示各个站的标识符和相应的标识符之间的对应关系 网络在相应的地址位置。