公开(公告)号：US06574746B1

公开(公告)日：2003-06-03

申请号：US09347117

申请日：1999-07-02

申请人： Tayung Wong ,  Ashok Singhal ,  Clement Fang ,  John Carrillo ,  Han Y. Ko

发明人： Tayung Wong ,  Ashok Singhal ,  Clement Fang ,  John Carrillo ,  Han Y. Ko

IPC分类号： G06F1108

CPC分类号： G06F11/1012 ,  G06F11/102

摘要： A system and method for storing error correction check words in computer memory modules. Check bits stored in physically adjacent locations within a dynamic random access memory (DRAM) chip are assigned to different check words. By assigning check bits to check words in this manner, multi-bit soft errors resulting from errors in two or more check bits stored in physically adjacent memory locations will appear as single-bit errors to an error correction subsystem. Similarly, the likelihood of multi-bit errors occurring in the same check word may be reduced.

摘要翻译： 一种用于在计算机存储器模块中存储纠错检查词的系统和方法。 检查存储在动态随机存取存储器（DRAM）芯片内的物理相邻位置的位被分配给不同的检查字。 通过以这种方式分配校验位以检查字，存储在物理上相邻的存储器位置中的两个或更多个校验位中的错误导致的多位软错误将作为单位错误出现到纠错子系统。 类似地，可以减少在相同检查字中发生的多位错误的可能性。

公开(公告)号：US06683372B1

公开(公告)日：2004-01-27

申请号：US09442850

申请日：1999-11-18

申请人： Tayung Wong ,  John Carrillo ,  Jay Robinson ,  Clement Fang ,  David Jeffrey ,  Nikhil Vaidya ,  Nagaraj Mitty

发明人： Tayung Wong ,  John Carrillo ,  Jay Robinson ,  Clement Fang ,  David Jeffrey ,  Nikhil Vaidya ,  Nagaraj Mitty

IPC分类号： H01L2300

CPC分类号： G11C5/02 ,  G06F11/006 ,  G06F11/1024 ,  G11C5/04 ,  G11C8/12 ,  G11C11/40615 ,  G11C2029/4402 ,  H05K1/181

摘要： A memory expansion module with stacked memory packages. A memory module is implemented using stacked memory packages. Each of the stacked memory packages contains multiple memory chips, typically DRAMs (dynamic random access memory). The memory may be organized into multiple banks, wherein a given memory chip within a stacked memory package is part of one bank, while another memory chip in the same package is part of another bank. The memory module also includes a clock driver chip and a storage unit. The storage unit is configured to store module identification information, such as a serial number. The storage unit is also configured to store information correlating electrical contact pads on the module with individual signal pins on the stacked memory packages. This may allow an error to be quickly traced to a specific pin on a stacked memory package when an error is detected on the memory bus by an error correction subsystem.

摘要翻译： 具有堆叠内存包的内存扩展模块。 使用堆叠存储器包实现存储器模块。 每个堆叠的存储器包包含多个存储器芯片，通常是DRAM（动态随机存取存储器）。 存储器可以被组织成多个存储体，其中堆叠存储器封装内的给定存储器芯片是一个存储体的一部分，而同一封装中的另一个存储器芯片是另一个存储体的一部分。 存储器模块还包括时钟驱动器芯片和存储单元。 存储单元被配置为存储诸如序列号的模块识别信息。 存储单元还被配置为存储将模块上的电接触焊盘与堆叠的存储器封装上的各个信号引脚相关联的信息。 当误差校正子系统在存储器总线上检测到错误时，这可能允许将错误快速跟踪到堆叠存储器封装上的特定引脚。

公开(公告)号：US06414868B1

公开(公告)日：2002-07-02

申请号：US09327058

申请日：1999-06-07

申请人： Tayung Wong ,  John Carrillo ,  Jay Robinson ,  Clement Fang

发明人： Tayung Wong ,  John Carrillo ,  Jay Robinson ,  Clement Fang

IPC分类号： G11C502

CPC分类号： G11C5/06 ,  G11C5/04

摘要： A memory expansion module including multiple memory banks and a bank control circuit is disclosed. In one embodiment, a memory module includes a printed circuit board with a connector edge adapted for insertion in an expansion socket of a computer system. Mounted upon the circuit board is a plurality of memory chips, typically Dynamic Random Access Memory (DRAM) chips, which make up an upper bank and a lower bank of memory. A buffer circuit is mounted upon the printed circuit board, for the purpose of driving address signals, Column Address Strobe (CAS) signals, and write enable signals to each of the memory chips. Also mounted upon the printed circuit board is a bank control circuit, which is coupled to the memory chips. An address signal is used as a bank selection input to the bank control circuit, which will drive Row Address Strobe (RAS) signals to the memory chips of the selected memory bank. The bank control circuit is further configured to drive RAS signals to both banks simultaneously during CBR (CAS before RAS) refresh operations, which occur when a CAS signal is asserted before a RAS signal.

摘要翻译： 公开了一种包括多个存储体和存储体控制电路的存储器扩展模块。 在一个实施例中，存储器模块包括具有适于插入计算机系统的扩展插座中的连接器边缘的印刷电路板。 安装在电路板上的是多个存储器芯片，通常是动态随机存取存储器（DRAM）芯片，其构成上部存储器和较低存储器组。 缓冲电路安装在印刷电路板上，用于驱动地址信号，列地址选通（CAS）信号和写使能信号到每个存储器芯片。 也安装在印刷电路板上的是与存储器芯片耦合的存储体控制电路。 地址信号被用作对存储体控制电路的存储体选择输入，其将将行地址选通（RAS）信号驱动到所选存储体的存储器芯片。 银行控制电路还被配置为在CBR（RAS之前的CAS）刷新操作期间同时向两个存储体驱动RAS信号，这在CAS信号在RAS信号之前被断言时发生。

公开(公告)号：US20050058001A1

公开(公告)日：2005-03-17

申请号：US10661872

申请日：2003-09-12

申请人： Tayung Wong ,  Clement Fang ,  David Jeffrey ,  Neil Duncan

发明人： Tayung Wong ,  Clement Fang ,  David Jeffrey ,  Neil Duncan

IPC分类号： G06F12/06 ,  G06F13/42 ,  G11C5/04 ,  G11C8/00 ,  G11C8/12

CPC分类号： G06F13/4243 ,  G06F12/0653 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A memory module for use in a two rank memory module system includes a plurality of memory devices and a control circuit. In one embodiment, the control circuit may be configured to generate a chip select signal that is provided to each of the memory devices. The chip select signal may be dependent upon assertions of a first bank chip select signal and a second bank chip select signal received from a memory controller. The control circuit may be further configured to generate an address signal that is provided to each of the memory devices. The address signal may be asserted dependent upon which of the first bank chip select signal and the second bank chip select signal are asserted.

摘要翻译： 用于二级存储器模块系统的存储器模块包括多个存储器件和控制电路。 在一个实施例中，控制电路可以被配置为产生提供给每个存储器件的片选信号。 芯片选择信号可以取决于从存储器控制器接收到的第一组片选择信号和第二组片选择信号的断言。 控制电路还可以被配置为产生提供给每个存储器件的地址信号。 取决于第一组芯片选择信号和第二组片选择信号中的哪一个被断言地址信号。