公开(公告)号：US08362545B2

公开(公告)日：2013-01-29

申请号：US13064344

申请日：2011-03-21

申请人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L27/11524

摘要： The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer.

公开(公告)号：US20120068249A1

公开(公告)日：2012-03-22

申请号：US13064344

申请日：2011-03-21

申请人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L27/11524

摘要： The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer.

摘要翻译： 非易失性存储器件包括半导体衬底和限定半导体衬底中的有源区的器件隔离层。 器件隔离层包括比半导体衬底的顶表面低的顶表面，使得有源区的侧上表面被暴露。 感测线与有源区和器件隔离层交叉，并且与感测线间隔开的字线与有源区和器件隔离层交叉。

公开(公告)号：US20100171168A1

公开(公告)日：2010-07-08

申请号：US12648386

申请日：2009-12-29

申请人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L29/788 ,  H01L21/762

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/76224 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory device includes an active region in which a channel of a transistor is formed in a substrate, element isolation films defining the active region and formed on the substrate at both sides of the channel at a height lower than an upper surface of the active region, a first dielectric layer, a second dielectric layer, and a control gate electrode formed on the active region in this order, and a floating gate electrode formed between the first dielectric layer and the second dielectric layer so as to intersect the length direction of the channel and extend to the upper surfaces of the element isolation films at both sides of the channel, thereby surrounding the channel.

摘要翻译： 非易失性存储器件包括其中在衬底中形成晶体管的沟道的有源区，限定有源区的元件隔离膜，并且形成在通道两侧的基底上，高度低于 有源区，第一电介质层，第二电介质层和控制栅电极，以及在第一介电层和第二电介质层之间形成的与栅极的长度相交的浮栅， 通道的方向并延伸到通道两侧的元件隔离膜的上表面，从而围绕通道。

公开(公告)号：US08604535B2

公开(公告)日：2013-12-10

申请号：US12648386

申请日：2009-12-29

申请人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L29/788 ,  H01L21/762

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/76224 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory device includes an active region in which a channel of a transistor is formed in a substrate, element isolation films defining the active region and formed on the substrate at both sides of the channel at a height lower than an upper surface of the active region, a first dielectric layer, a second dielectric layer, and a control gate electrode formed on the active region in this order, and a floating gate electrode formed between the first dielectric layer and the second dielectric layer so as to intersect the length direction of the channel and extend to the upper surfaces of the element isolation films at both sides of the channel, thereby surrounding the channel.

摘要翻译： 非易失性存储器件包括其中在衬底中形成晶体管的沟道的有源区，限定有源区的元件隔离膜，并且形成在通道两侧的基底上，高度低于 有源区，第一电介质层，第二电介质层和控制栅电极，以及在第一介电层和第二电介质层之间形成的与栅极的长度相交的浮栅， 通道的方向并延伸到通道两侧的元件隔离膜的上表面，从而围绕通道。

公开(公告)号：US20090121277A1

公开(公告)日：2009-05-14

申请号：US12289297

申请日：2008-10-24

申请人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L27/115

CPC分类号： H01L27/11521 ,  H01L27/11519 ,  H01L27/11524

摘要： The nonvolatile memory device includes a semiconductor substrate, and a device isolation layer defining an active region in the semiconductor substrate. The device isolation layer includes a top surface lower than a top surface of the semiconductor substrate, such that a side-upper surface of the active region is exposed. A sense line crosses both the active region and the device isolation layer, and a word line, spaced apart from the sense line, crosses both the active region and the device isolation layer.

摘要翻译： 非易失性存储器件包括半导体衬底和限定半导体衬底中的有源区的器件隔离层。 器件隔离层包括比半导体衬底的顶表面低的顶表面，使得有源区的侧上表面被暴露。 感测线与有源区和器件隔离层交叉，并且与感测线间隔开的字线与有源区和器件隔离层交叉。

公开(公告)号：US20090121276A1

公开(公告)日：2009-05-14

申请号：US12267679

申请日：2008-11-10

申请人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Tea-Kwang Yu ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile memory device includes a substrate, a device isolation region disposed in the substrate and abutting a sidewall of an active region defined in the substrate, the device isolation region having a recessed portion and a word line crossing the active region and the recessed portion of the device isolation region and conforming to the sidewall adjacent the recessed portion of the device isolation region. The nonvolatile memory device may further include a sense line crossing the active region and the device isolation region parallel to the word line, the sense line overlying a portion of the device isolation region having a top surface at substantially the same level as a top surface of the active region. An edge of the active region adjacent the sidewall may be rounded.

摘要翻译： 非易失性存储器件包括衬底，器件隔离区域，设置在衬底中并邻接限定在衬底中的有源区域的侧壁，器件隔离区域具有与有源区域交叉的凹陷部分和字线，凹部 器件隔离区域并且与邻近器件隔离区域的凹部的侧壁一致。 非易失性存储器件还可以包括与激活区域和器件隔离区域平行于字线交叉的检测线，覆盖器件隔离区域的一部分的感测线具有与顶表面基本相同的水平的顶表面 活跃区域。 邻近侧壁的有源区域的边缘可以是圆形的。

公开(公告)号：US09312184B2

公开(公告)日：2016-04-12

申请号：US14200274

申请日：2014-03-07

申请人： Tea-Kwang Yu ,  Bae-Seong Kwon ,  Yong-Tae Kim ,  Chul-Ho Chung ,  Yong-Suk Choi

发明人： Tea-Kwang Yu ,  Bae-Seong Kwon ,  Yong-Tae Kim ,  Chul-Ho Chung ,  Yong-Suk Choi

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L21/823462 ,  H01L21/823456 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881

摘要： In a method of manufacturing a semiconductor device, a split gate structure is formed on a cell region of a substrate including the cell region and a logic region. The logic region has a high voltage region, an ultra high voltage region and a low voltage region, and the split gate structure includes a first gate insulation layer pattern, a floating gate, a tunnel insulation layer pattern and a control gate. A spacer layer is formed on the split gate structure and the substrate. The spacer layer is etched to form a spacer on a sidewall of the split gate structure and a second gate insulation layer pattern on the ultra high voltage region of the substrate. A gate electrode is formed on each of the high voltage region of the substrate, the second gate insulation layer pattern, and the low voltage region of the substrate.

摘要翻译： 在制造半导体器件的方法中，在包括单元区域和逻辑区域的衬底的单元区域上形成分离栅极结构。 逻辑区域具有高电压区域，超高压区域和低电压区域，并且分离栅极结构包括第一栅极绝缘层图案，浮动栅极，隧道绝缘层图案和控制栅极。 在分离栅极结构和衬底上形成间隔层。 蚀刻间隔层以在分离栅极结构的侧壁上形成间隔物，并在衬底的超高电压区域上形成第二栅极绝缘层图案。 在基板的高电压区域，第二栅极绝缘层图案和基板的低电压区域中的每一个上形成栅电极。

公开(公告)号：US20120070949A1

公开(公告)日：2012-03-22

申请号：US13180613

申请日：2011-07-12

申请人： Tea-Kwang Yu ,  Byung-Sup Shim ,  Yong-Kyu Lee ,  Bo-Young Seo ,  Yong-Tae Kim

发明人： Tea-Kwang Yu ,  Byung-Sup Shim ,  Yong-Kyu Lee ,  Bo-Young Seo ,  Yong-Tae Kim

IPC分类号： H01L21/8239 ,  H01L21/8229

CPC分类号： H01L27/2436 ,  H01L27/105 ,  H01L27/2445 ,  H01L45/1683

摘要： A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region.

摘要翻译： 一种制造半导体器件的方法包括提供具有存储块和在其中定义的逻辑块的衬底，在存储块上形成伪栅极图案; 在伪栅极图案的一侧形成第一导电类型的第一区域和在虚拟栅极图案的另一侧形成第二导电类型的第二区域，以及形成与第一区域电连接的非易失性存储器件。

公开(公告)号：US08476130B2

公开(公告)日：2013-07-02

申请号：US13180613

申请日：2011-07-12

申请人： Tea-Kwang Yu ,  Byung-Sup Shim ,  Yong-Kyu Lee ,  Bo-Young Seo ,  Yong-Tae Kim

发明人： Tea-Kwang Yu ,  Byung-Sup Shim ,  Yong-Kyu Lee ,  Bo-Young Seo ,  Yong-Tae Kim

IPC分类号： H01L21/8238

CPC分类号： H01L27/2436 ,  H01L27/105 ,  H01L27/2445 ,  H01L45/1683

摘要： A method of fabricating a semiconductor device includes providing a substrate having a memory block and a logic block defined therein, forming a dummy gate pattern on the memory block; forming a first region of a first conductivity type at one side of the dummy gate pattern and a second region of a second conductivity type at the other side of the dummy gate pattern, and forming a nonvolatile memory device electrically connected to the first region.

摘要翻译： 一种制造半导体器件的方法包括提供具有存储块和在其中定义的逻辑块的衬底，在存储块上形成伪栅极图案; 在伪栅极图案的一侧形成第一导电类型的第一区域和在虚拟栅极图案的另一侧形成第二导电类型的第二区域，以及形成与第一区域电连接的非易失性存储器件。

公开(公告)号：US08059473B2

公开(公告)日：2011-11-15

申请号：US12844234

申请日：2010-07-27

申请人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

发明人： Hee-Seog Jeon ,  Seung-Beom Yoon ,  Jeong-Uk Han ,  Yong-Tae Kim

IPC分类号： G11C11/34

CPC分类号： H01L27/11521 ,  G11C16/0425 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/42328

摘要： A non-volatile memory device includes a floating gate formed on a substrate with a gate insulation layer interposed therebetween, a tunnel insulation layer formed on the floating gate, a select gate electrode inducing charge introduction through the gate insulation layer, and a control gate electrode inducing charge tunneling occurring through the tunnel insulation layer. The select gate electrode is insulated from the control gate electrode. According to the non-volatile memory device, a select gate electrode and a control gate electrode are formed on a floating gate, and thus a voltage is applied to the respective gate electrodes to write and erase data.

摘要翻译： 非易失性存储器件包括形成在衬底上的栅极绝缘层之间的浮置栅极，形成在浮置栅极上的隧道绝缘层，通过栅极绝缘层引入电荷的选择栅极电极和控制栅电极 通过隧道绝缘层引起电荷隧穿。 选择栅电极与控制栅电极绝缘。 根据非易失性存储器件，在浮动栅极上形成选择栅电极和控制栅电极，从而向相应的栅电极施加电压以写入和擦除数据。