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公开(公告)号：US06493257B1
公开(公告)日：2002-12-10
申请号：US10108687
申请日：2002-03-27
IPC分类号： G11C11412
CPC分类号： G11C14/00
摘要： A state saving circuit and method for using the same. The circuit comprises a first latch powered by an uninterrupted power supply, wherein the first latch includes a first pair of cross coupled inverters for storing data, and includes an input cut-off control for isolating the data in the first pair of cross coupled inverters; a second latch coupled to an output of the first latch and powered by an interruptible power supply, wherein the second latch includes a second pair of cross coupled inverters and a clock input for latching the data from the first latch to the second latch; and wherein an interruption of power to the second latch results in a state being saved in the first latch.
摘要翻译： 一种状态保存电路及其使用方法。 电路包括由不间断电源供电的第一锁存器，其中第一锁存器包括用于存储数据的第一对交叉耦合的反相器，并且包括用于隔离第一对交叉耦合的反相器中的数据的输入截止控制; 耦合到所述第一锁存器的输出并由可中断电源供电的第二锁存器，其中所述第二锁存器包括第二对交叉耦合的反相器和用于将所述数据从所述第一锁存器锁存到所述第二锁存器的时钟输入; 并且其中对所述第二锁存器的电力中断导致在所述第一锁存器中保存状态。
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2.发明授权Low power LSSD flip flops and a flushable single clock splitter for flip flops 失效低功率LSSD触发器和可触发单触发器的单个时钟分配器公开(公告)号：US06304122B1
公开(公告)日：2001-10-16
申请号：US09641425
申请日：2000-08-17
IPC分类号： H03K3289
CPC分类号： H03K3/0375 , H03K3/0372
摘要： This invention reduces power in flip flop apparatuses by providing flip flop apparatuses that have fewer clock trees than prior art flip flops yet still support some or all of the Level Sensitive Scan Design (LSSD) functionality. In preferred embodiments of the present invention, one clock tree is used instead of two to provide lower power, and less switching devices in clocks splitters are used, which also provides lower power. Additionally, a flushable single clock splitter is provided that allows one clock tree to be used up to the flushable single clock splitter and provides two clocks on the output of the flushable single clock splitter. This saves some power yet still allows for dual clock flip flop designs.
摘要翻译： 本发明通过提供具有比现有技术的触发器更少的时钟树的触发器装置来降低触发器装置的功率，但仍然支持一些或全部级别敏感扫描设计（LSSD）功能。 在本发明的优选实施例中，使用一个时钟树来代替两个时钟树来提供较低的功率，并且使用时钟分配器中的较少的开关器件，其也提供较低的功率。 另外，提供了一个可冲洗的单时钟分离器，其允许一个时钟树被使用到可冲洗的单时钟分离器，并且在可冲洗单时钟分离器的输出端上提供两个时钟。 这节省了一些功耗，但仍然允许双时钟触发器设计。
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公开(公告)号：US06661121B2
公开(公告)日：2003-12-09
申请号：US09955772
申请日：2001-09-19
IPC分类号： H03K300
摘要： A pulse generation circuit delivers an output pulse whose width is tailored to the load. The pulse generation circuit comprises the following components. A drive circuit has an input coupled to receive a clock signal and an output coupled to drive a load. A comparator has an input coupled to the output of the drive circuit. Another input of the comparator is supplied by a reference voltage. A feedback circuit comprises logic gates and is coupled between the output of the comparator and the input of the drive circuit. The feedback circuit terminates a pulse output from the drive circuit when the pulse voltage output from the drive circuit exceeds the reference voltage. The reference voltage is higher than a voltage required to trigger the logic gates and a voltage required to drive the load. This ensures that the load is driven adequately over a wide range of load currents and capacitances. By setting the reference voltage between the voltage required to drive the load and the supply voltage, the pulse width is not excessive.
摘要翻译： 脉冲发生电路提供输出脉冲，其宽度适应负载。 脉冲发生电路包括以下部件。 驱动电路具有耦合以接收时钟信号的输入和耦合以驱动负载的输出。 比较器具有耦合到驱动电路的输出的输入。 比较器的另一个输入端由参考电压提供。 反馈电路包括逻辑门并耦合在比较器的输出端和驱动电路的输入端之间。 当从驱动电路输出的脉冲电压超过参考电压时，反馈电路终止来自驱动电路的脉冲输出。 参考电压高于触发逻辑门所需的电压和驱动负载所需的电压。 这确保了负载在宽范围的负载电流和电容上充分驱动。 通过设置驱动负载所需的电压与电源电压之间的参考电压，脉冲宽度不会过大。
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公开(公告)号：US6037677A
公开(公告)日：2000-03-14
申请号：US321894
申请日：1999-05-28
IPC分类号： H01L23/498 , H02J1/00
CPC分类号： H01L23/49838 , H01L2924/0002 , H01L2924/3011 , Y10T307/50
摘要： A connection array for a chip provides a substantial increase in numbers of signal connection locations and a power distribution arrangement of improved robustness and noise immunity while accommodating multiple power supply voltages by providing pairs of sub-arrays aligned with chip edges and signal connection locations formed in columns orthogonal to a chip edge or segment of the chip perimeter. Signal connections in a column are spaced at a first pitch and columns of signal connections are spaced at a second pitch. Power connections corresponding to different power supply voltages are provided between columns of signal connections and along rows which are centered between rows of signal connections generally parallel to an edge of a chip. Power distribution layers may be formed as a mesh which extends in under the chip in alignment with power connections to the chip and beyond the perimeter of the chip, as well to provide multiple low-impedance power delivery paths to improve noise immunity. The connection pattern allows fewer layers of redistribution wiring to be used to escape the chip, reducing overall product cost. Thus improvements in functionality and performance can be supported at reduced cost, particularly for custom designed application specific integrated circuits.
摘要翻译： 用于芯片的连接阵列通过提供与芯片边缘对准的一对子阵列和形成在其中的信号连接位置而提供了大量增加的信号连接位置数量和功率分配布置，其具有改进的鲁棒性和抗噪声性，同时容纳多个电源电压 与芯片边缘或芯片周边的片段正交的列。 列中的信号连接以第一间距间隔开，并且信号连接列以第二间距间隔开。 对应于不同电源电压的电源连接提供在信号连接的列之间，并且沿着大体上平行于芯片的边缘的信号连接的行之间的行居中。 功率分配层可以形成为在芯片下方延伸的网格，其与芯片的功率连接对准并且超过芯片的周边，并且提供多个低阻抗功率传递路径以改善抗噪声性。 连接图案允许使用较少的再分配布线层来逸出芯片，从而降低整体产品成本。 因此，可以以降低的成本支持功能和性能的改进，特别是对于定制设计的专用集成电路。
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公开(公告)号：US06609228B1
公开(公告)日：2003-08-19
申请号：US09713571
申请日：2000-11-15
申请人： Paul H. Bergeron , Keith M. Carrig , Alvar A. Dean , Roger P. Gregor , David J. Hathaway , David E. Lackey , Harold E. Reindel , Larry Wissel
发明人： Paul H. Bergeron , Keith M. Carrig , Alvar A. Dean , Roger P. Gregor , David J. Hathaway , David E. Lackey , Harold E. Reindel , Larry Wissel
IPC分类号： G06F1750
CPC分类号： G06F17/5072 , G06F2217/78
摘要： A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected; changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster; and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.
摘要翻译： 时钟优化的方法和结构，包括根据时钟信号要求创建时钟馈电电路的初始放置; 识别所述时钟馈送电路的簇，其中每个簇包括与所述簇内的每个时钟馈送电路连接的不同的时钟信号供应装置; 改变时钟馈电电路和时钟信号供应装置之间的引脚连接，以将选定的时钟馈电电路切换到不同的簇，以减少时钟馈送电路和每个集群内的时钟信号供应装置之间的导线长度; 以及在设计约束内调整时钟馈电电路的位置，以进一步减少电线的长度。
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公开(公告)号：US06335494B1
公开(公告)日：2002-01-01
申请号：US09602911
申请日：2000-06-23
申请人： Roger P. Gregor , James P. Libous
发明人： Roger P. Gregor , James P. Libous
IPC分类号： H01R1204
CPC分类号： H05K1/0216 , H01L23/49822 , H01L23/50 , H01L2924/0002 , H05K1/0262 , H05K2201/093 , H05K2201/09663 , H01L2924/00
摘要： Power layers of a multi-layer connection structure forming a power distribution network are partitioned to accommodate all necessary voltages for one or more chips connected thereto in each power layer. By doing so, and rearranging vias as permitted by such partitioning via length is reduced while via numbers can be increased to reduce self-inductance of the structure. Transmission lines formed by conductors in the signal layers are referenced to the correct power supply and return/image currents are made of similar path length and substantially symmetrical for both positive- and negative-going signal transitions. These effects reduce delta-I noise to levels which preserve good signal-to-noise ratios to current and foreseeable reduced signal levels.
摘要翻译： 形成配电网络的多层连接结构的功率层被分割以适应在每个功率层中连接到其上的一个或多个芯片的所有必要电压。 通过这样做，并且通过长度的这种分割允许的重新布置过孔减小，同时可以增加数字以减少结构的自感。 由信号层中的导体形成的传输线参考正确的电源，并且返回/图像电流由相似的路径长度构成，对于正向和负向信号转换都是基本对称的。 这些效应可以将Delta-I噪声降低到与当前和可预见的降低的信号电平保持良好的信噪比的电平。
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公开(公告)号：US06204713B1
公开(公告)日：2001-03-20
申请号：US09224779
申请日：1999-01-04
IPC分类号： G06F104
CPC分类号： G06F17/5077 , G06F1/10 , G06F2217/62
摘要： An integrated circuit chip comprises a plurality of clock distribution sub-networks each including a clock input for receiving a clock signal, each of the clock distribution sub-networks having a capacitance, as seen from the clock input, substantially equivalent to others of the clock distribution sub-networks; and a structured clock buffer having a size based on a load of the clock distribution sub-networks, and providing the clock signal to the clock distribution sub-networks.
摘要翻译： 集成电路芯片包括多个时钟分配子网络，每个时钟分配子网络包括用于接收时钟信号的时钟输入，每个时钟分配子网络具有从时钟输入看的电容，其基本上等于时钟的其他时钟 分销子网; 以及具有基于时钟分配子网络的负载的大小的结构化时钟缓冲器，并且将时钟信号提供给时钟分配子网络。
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公开(公告)号：US5084637A
公开(公告)日：1992-01-28
申请号：US358321
申请日：1989-05-30
申请人： Roger P. Gregor
发明人： Roger P. Gregor
IPC分类号： H03K19/0185
CPC分类号： H03K19/018592
摘要： A bidirectional level shifting interface circuit has first and second I/O ports and an FET with a drain-source channel connected between the first and second I/O ports. The first I/O port is connected to an I/O port of a first digital circuit operating at a relatively low supply voltage, and the second I/O port is connected to an I/O port of a second digital circuit operating at a relatively high supply voltage. This channel passes communication signals in each direction between the first and second digital circuit. A latching circuit comprising a P Channel FET is biased by the relatively high voltage supply, has an output connected to the second I/O port, and has a control input. The interface circuit further comprises an inverter circuit having a control input connected to the second I/O port and an inverted output connected to the control input of the latching FET such that when the second I/O port exhibits a binary one voltage caused by the first digital circuit, the inverted output exhibits a binary zero voltage to activate the P Channel FET to latch the second I/O port at sufficient voltage to drive the second digital circuit at binary one level.
摘要翻译： 双向电平移位接口电路具有第一和第二I / O端口以及连接在第一和第二I / O端口之间的漏极 - 源极通道的FET。 第一I / O端口连接到在较低电源电压下工作的第一数字电路的I / O端口，而第二I / O端口连接到第二数字电路的I / O端口 电源电压相对较高。 该通道在第一和第二数字电路之间的每个方向上通过通信信号。 包括P沟道FET的锁存电路被相对高的电压源偏置，具有连接到第二I / O端口的输出，并具有控制输入。 接口电路还包括具有连接到第二I / O端口的控制输入和连接到锁存FET的控制输入的反相输出的反相器电路，使得当第二I / O端口呈现由 第一数字电路，反相输出显示二进制零电压以激活P沟道FET以在足够的电压下锁存第二I / O端口，以二进制一级驱动第二数字电路。
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