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52 条记录 (耗时 0.028 秒)

    CMOS state saving latch
    1.
    发明授权
    CMOS state saving latch 失效
    CMOS状态保存锁存器

    公开(公告)号：US06493257B1

    公开(公告)日：2002-12-10

    申请号：US10108687

    申请日：2002-03-27

    申请人： Terry C. Coughlin, Jr. ,  Roger P. Gregor ,  Steven F. Oakland ,  Douglas W. Stout

    发明人： Terry C. Coughlin, Jr. ,  Roger P. Gregor ,  Steven F. Oakland ,  Douglas W. Stout

    IPC分类号： G11C11412

    CPC分类号： G11C14/00

    摘要： A state saving circuit and method for using the same. The circuit comprises a first latch powered by an uninterrupted power supply, wherein the first latch includes a first pair of cross coupled inverters for storing data, and includes an input cut-off control for isolating the data in the first pair of cross coupled inverters; a second latch coupled to an output of the first latch and powered by an interruptible power supply, wherein the second latch includes a second pair of cross coupled inverters and a clock input for latching the data from the first latch to the second latch; and wherein an interruption of power to the second latch results in a state being saved in the first latch.

    摘要翻译： 一种状态保存电路及其使用方法。 电路包括由不间断电源供电的第一锁存器，其中第一锁存器包括用于存储数据的第一对交叉耦合的反相器，并且包括用于隔离第一对交叉耦合的反相器中的数据的输入截止控制; 耦合到所述第一锁存器的输出并由可中断电源供电的第二锁存器，其中所述第二锁存器包括第二对交叉耦合的反相器和用于将所述数据从所述第一锁存器锁存到所述第二锁存器的时钟输入; 并且其中对所述第二锁存器的电力中断导致在所述第一锁存器中保存状态。

    Low power LSSD flip flops and a flushable single clock splitter for flip flops
    2.
    发明授权
    Low power LSSD flip flops and a flushable single clock splitter for flip flops 失效
    低功率LSSD触发器和可触发单触发器的单个时钟分配器

    公开(公告)号：US06304122B1

    公开(公告)日：2001-10-16

    申请号：US09641425

    申请日：2000-08-17

    申请人： Roger P. Gregor ,  Steven F. Oakland ,  Toshiharu Saitoh ,  Sebastian T. Ventrone

    发明人： Roger P. Gregor ,  Steven F. Oakland ,  Toshiharu Saitoh ,  Sebastian T. Ventrone

    IPC分类号： H03K3289

    CPC分类号： H03K3/0375 ,  H03K3/0372

    摘要： This invention reduces power in flip flop apparatuses by providing flip flop apparatuses that have fewer clock trees than prior art flip flops yet still support some or all of the Level Sensitive Scan Design (LSSD) functionality. In preferred embodiments of the present invention, one clock tree is used instead of two to provide lower power, and less switching devices in clocks splitters are used, which also provides lower power. Additionally, a flushable single clock splitter is provided that allows one clock tree to be used up to the flushable single clock splitter and provides two clocks on the output of the flushable single clock splitter. This saves some power yet still allows for dual clock flip flop designs.

    摘要翻译： 本发明通过提供具有比现有技术的触发器更少的时钟树的触发器装置来降低触发器装置的功率，但仍然支持一些或全部级别敏感扫描设计（LSSD）功能。 在本发明的优选实施例中，使用一个时钟树来代替两个时钟树来提供较低的功率，并且使用时钟分配器中的较少的开关器件，其也提供较低的功率。 另外，提供了一个可冲洗的单时钟分离器，其允许一个时钟树被使用到可冲洗的单时钟分离器，并且在可冲洗单时钟分离器的输出端上提供两个时钟。 这节省了一些功耗，但仍然允许双时钟触发器设计。

    High performance state saving circuit
    3.
    发明授权
    High performance state saving circuit 失效
    高性能状态保存电路

    公开(公告)号：US06927614B2

    公开(公告)日：2005-08-09

    申请号：US10605750

    申请日：2003-10-23

    申请人： Steven F. Oakland ,  Douglas W. Stout

    发明人： Steven F. Oakland ,  Douglas W. Stout

    IPC分类号： H03K3/356 ,  H03K3/289

    CPC分类号： H03K3/356008

    摘要： A state saving circuit includes a state saving latch powered by an un-interruptible power supply, and a cut-off control device powered by the un-interruptible power supply that selectively connects the state saving latch to a pair of latch nodes based upon a control signal. The control signal determines whether the state-saving latch is in one of a state saving mode and a state restoring mode.

    摘要翻译： 状态保存电路包括由不可中断电源供电的状态保存锁存器以及由不可中断电源供电的截止控制装置，其基于控制将选择性地将状态保存锁存器连接到一对锁存器节点 信号。 控制信号确定状态保持锁存器是否处于状态保存模式和状态恢复模式之一。

    Clock generator having improved deskewer
    4.
    发明授权
    Clock generator having improved deskewer 失效
    时钟发生器具有改进的电锯

    公开(公告)号：US07456674B2

    公开(公告)日：2008-11-25

    申请号：US12027467

    申请日：2008-02-07

    申请人： Steven F. Oakland

    发明人： Steven F. Oakland

    IPC分类号： G06F1/04

    CPC分类号： H03K5/15013 ,  G06F1/10

    摘要： Disclosed is a clock generation circuit for generating a clock-out signal that has a fixed latency with respect to a clock-input signal. When multiple such clock generation circuits are utilized to feed clock signals to different digital logic circuits within an integrated circuit structure, differences in delay time, referred to as skew, are minimized. An embodiment of the clock generation circuit incorporates a waveform generator and a timing-improved deskewer. The waveform generator is clocked by a clock-in signal. The deskewer comprises a flip-flop, a level-sensitive latch, and a multiplexer. The flip-flop and latch are connected in parallel and each receives waveform signals from the waveform generator as well as the clock-in signal in order to generate output signals. The multiplexer gates the flip-flop and latch output signals with the clock-in signal in order to generate the clock-out signal. A testable deskewer for edge-sensitive multiplexer scan designs is also disclosed.

    摘要翻译： 公开了一种用于产生相对于时钟输入信号具有固定等待时间的时钟输出信号的时钟发生电路。 当使用多个这样的时钟发生电路将时钟信号馈送到集成电路结构内的不同数字逻辑电路时，延迟时间差（称为偏斜）被最小化。 时钟发生电路的一个实施例包括波形发生器和时序改进的电机。 波形发生器由时钟输入信号计时。 该台式电脑包括触发器，电平敏感锁存器和多路复用器。 触发器和锁存器并联连接，并且每个接收来自波形发生器的波形信号以及时钟输入信号，以便产生输出信号。 多路复用器使用触发器门锁定输出信号并输入时钟输入信号，以产生时钟输出信号。 还公开了用于边缘敏感多路复用器扫描设计的可​​测试的台式电脑。

    Testable passgate logic circuits
    7.
    发明授权
    Testable passgate logic circuits 失效
    可测通路逻辑电路

    公开(公告)号：US4868413A

    公开(公告)日：1989-09-19

    申请号：US183865

    申请日：1988-04-20

    申请人： Steven F. Oakland ,  Clarence R. Ogilvie

    发明人： Steven F. Oakland ,  Clarence R. Ogilvie

    IPC分类号： G01R31/317 ,  G01R31/28 ,  H03K17/00 ,  H03K17/693

    CPC分类号： H03K17/693

    摘要： A logic circuit is provided which includes a multiplexer having a plurality of parallelly arranged channels, each channel including a switching device having a control element and responsive to a first control signal, a plurality of signal terminals, a common terminal, each of the channels being connected between a respective one of the plurality of signal terminals and the common terminal, and a termination circuit which includes a series circuit having a plurality of switching devices, each having a control element and being responsive to a second control signal. The control elements of each of the plurality of switching devices of the series circuit are coupled to a respective one of the control elements of the switching devices of the channels so that when one of the switching devices of the series circuit is turned on, the respective one of the switching devices of the channels is turned off, and vice versa.

    Dense register array for enabling scan out observation of both L1 and L2 latches
    9.
    发明授权
    Dense register array for enabling scan out observation of both L1 and L2 latches 有权
    密码寄存器阵列，用于扫描L1和L2锁存器的观察

    公开(公告)号：US08423844B2

    公开(公告)日：2013-04-16

    申请号：US13004104

    申请日：2011-01-11

    申请人： Pamela S. Gillis ,  David E. Lackey ,  Steven F. Oakland ,  Jeffery H. Oppold

    发明人： Pamela S. Gillis ,  David E. Lackey ,  Steven F. Oakland ,  Jeffery H. Oppold

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318541

    摘要： A scannable register array structure includes a plurality of individual latches, each configured to hold one bit of array data in a normal mode of operation. The plurality of individual latches operate in scannable latch pairs in a test mode of operation, with first latches of the scannable latch pairs comprising L1 latches and second latches of the scannable latch pairs comprising L2 latches. A test clock signal generates a first clock pulse signal, A, for the L1 latches and a second clock pulse signal, B, for the L2 latches. The L2 latches are further configured to selectively receive L1 data therein upon a separate activation of the B clock signal, independent of the test clock signal, such that a scan out operation of the individual latches results in observation of L1 latch data.

    摘要翻译： 可扫描寄存器阵列结构包括多个单独锁存器，每个锁存器被配置为在正常操作模式下保持一位数组数组。 多个单独的锁存器在测试操作模式下以可扫描的锁存器对操作，可扫描锁存器对的第一锁存器包括包括L2锁存器的可扫描锁存器对的L1锁存器和第二锁存器。 测试时钟信号为L1锁存器产生第一时钟脉冲信号A，为L2锁存器产生第二时钟脉冲信号B。 L2锁存器还被配置为在独立于测试时钟信号的B时钟信号的单独激活之后有选择地接收L1数据，使得各个锁存器的扫描输出操作导致观察L1锁存器数据。

    Hold transition fault model and test generation method
    10.
    发明授权
    Hold transition fault model and test generation method 有权
    保持转换故障模型和测试生成方法

    公开(公告)号：US08181135B2

    公开(公告)日：2012-05-15

    申请号：US12548977

    申请日：2009-08-27

    申请人： Vikram Iyengar ,  Pamela S. Gillis ,  David E. Lackey ,  Steven F. Oakland

    发明人： Vikram Iyengar ,  Pamela S. Gillis ,  David E. Lackey ,  Steven F. Oakland

    IPC分类号： G06F17/50

    CPC分类号： G01R31/318357 ,  G01R31/318328

    摘要： A method of hold fault modeling and test generation. The method includes first modeling a fast-to-rise and a fast-to-fall hold fault for a plurality of circuit nets. Testing a fast-to-rise hold fault is accomplished by: setting up a logic value on each of the plurality of circuit nodes to 0; transitioning each of the plurality of circuit nodes from 0 to 1 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 0 to 1. Testing a fast-to-fall hold is accomplished by: setting up a logic value on each of the plurality circuit nodes to 1; transitioning each of the plurality of circuit nodes from 1 to 0 with a single clock pulse; and determining if at least one downstream node was inadvertently impacted by the transitioning from 1 to 0.

    摘要翻译： 一种保持故障建模和测试生成的方法。 该方法包括首先建模多个电路网络的快速上升和快速降档保持故障。 测试快速上升保持故障通过以下方式实现：将多个电路节点中的每一个上的逻辑值设置为0; 使用单个时钟脉冲将多个电路节点中的每一个从0转换到1; 以及确定至少一个下游节点是否被从0变为1的不期望的影响。通过以下方式来实现快速降档保持：通过在多个电路节点中的每一个上设置逻辑值到1; 使用单个时钟脉冲将多个电路节点中的每一个从1转换到0; 以及确定至少一个下游节点是否被从1到0的过渡中无意地影响。