公开(公告)号：US20080123622A1

公开(公告)日：2008-05-29

申请号：US11831073

申请日：2007-07-31

申请人： Teruo Kaganoi ,  Takeshi Aimoto

发明人： Teruo Kaganoi ,  Takeshi Aimoto

IPC分类号： H04L12/28

CPC分类号： H04L49/555 ,  H04L49/3009 ,  H04L49/351 ,  H04L49/354 ,  H04L49/557

摘要： A switching system includes a data collection device, one or more switching devices. The data collection device is for collection of first data subject to specific processing. The switching devices directly or indirectly connected to the data collection device. At least one of the switching devices includes a determination module that determines whether received data is the first data or is second data which is not subject to the specific processing, and a marking module that puts first marking on the received data determined to be the first data. The switching devices respectively includes a transferring processor that executes a first transfer process for sending the received data to the data collection device when the received data has the first marking, and a second transfer process that sends the received data to the specified destination when the received data does not have the first marking.

摘要翻译： 切换系统包括数据收集装置，一个或多个切换装置。 数据采集​​装置用于收集经受特定处理的第一数据。 交换设备直接或间接连接到数据采集设备。 至少一个切换装置包括：确定模块，其确定所接收的数据是否是第一数据，也可以是不受特定处理的第二数据;以及标记模块，其将接收到的数据确定为第一标记 数据。 交换设备分别包括传送处理器，当接收到的数据具有第一标记时，执行用于将接收到的数据发送到数据收集设备的第一传送处理;以及第二传送处理，当接收到的数据被接收时，将接收的数据发送到指定的目的地 数据没有第一个标记。

公开(公告)号：US09712449B2

公开(公告)日：2017-07-18

申请号：US13397292

申请日：2012-02-15

申请人： Naohisa Koie ,  Teruo Kaganoi ,  Takeshi Aimoto

发明人： Naohisa Koie ,  Teruo Kaganoi ,  Takeshi Aimoto

IPC分类号： H04L12/26 ,  H04L12/54 ,  H04L12/801 ,  H04L12/851

CPC分类号： H04L47/2441

摘要： It is intended to reduce a power consumption without degrading a communication quality of a packet transfer device. One or more of a receiver, a switch unit, and a transmitter include a QoS control circuit for applying QoS control to received packets. There is provided a power saving operation mode that enables power saving operation by changing a grain size of the QoS control according to a flow rate of the packets, and controlling whether or not to supply an electric power to the QoS control circuit or a part of the QoS control circuit, according to the flow rate of the packets.

公开(公告)号：US08340092B2

公开(公告)日：2012-12-25

申请号：US11831073

申请日：2007-07-31

申请人： Teruo Kaganoi ,  Takeshi Aimoto

发明人： Teruo Kaganoi ,  Takeshi Aimoto

IPC分类号： H04L12/28

CPC分类号： H04L49/555 ,  H04L49/3009 ,  H04L49/351 ,  H04L49/354 ,  H04L49/557

摘要： A switching system includes a data collection device, one or more switching devices. The data collection device is for collection of first data subject to specific processing. The switching devices directly or indirectly connected to the data collection device. At least one of the switching devices includes a determination module that determines whether received data is the first data or is second data which is not subject to the specific processing, and a marking module that puts first marking on the received data determined to be the first data. The switching devices respectively includes a transferring processor that executes a first transfer process for sending the received data to the data collection device when the received data has the first marking, and a second transfer process that sends the received data to the specified destination when the received data does not have the first marking.

摘要翻译： 切换系统包括数据收集装置，一个或多个切换装置。 数据采集​​装置用于收集经受特定处理的第一数据。 交换设备直接或间接连接到数据采集设备。 至少一个切换装置包括：确定模块，其确定所接收的数据是否是第一数据，也可以是不受特定处理的第二数据;以及标记模块，其将接收到的数据确定为第一标记 数据。 交换设备分别包括传送处理器，当接收到的数据具有第一标记时，执行用于将接收到的数据发送到数据收集设备的第一传送处理;以及第二传送处理，当接收到的数据被接收时，将接收的数据发送到指定的目的地 数据没有第一个标记。

公开(公告)号：US20120213075A1

公开(公告)日：2012-08-23

申请号：US13397292

申请日：2012-02-15

申请人： Naohisa Koie ,  Teruo Kaganoi ,  Takeshi Aimoto

发明人： Naohisa Koie ,  Teruo Kaganoi ,  Takeshi Aimoto

IPC分类号： H04L12/26

CPC分类号： H04L47/2441

摘要： It is intended to reduce a power consumption without degrading a communication quality of a packet transfer device. One or more of a receiver, a switch unit, and a transmitter include a QoS control circuit for applying QoS control to received packets. There is provided a power saving operation mode that enables power saving operation by changing a grain size of the QoS control according to a flow rate of the packets, and controlling whether or not to supply an electric power to the QoS control circuit or a part of the QoS control circuit, according to the flow rate of the packets.

摘要翻译： 旨在降低功耗而不降低分组传送装置的通信质量。 接收机，交换机单元和发射机中的一个或多个包括用于对接收的分组应用QoS控制的QoS控制电路。 提供了一种省电操作模式，其通过根据分组的流量改变QoS控制的粒度来进行节能操作，并且控制是否向QoS控制电路或部分服务提供电力 QoS控制电路，根据报文的流量。

公开(公告)号：US20120039184A1

公开(公告)日：2012-02-16

申请号：US13191981

申请日：2011-07-27

申请人： SHINICHI AKAHANE ,  Teruo Kaganoi ,  Tetsuya Nagata

发明人： SHINICHI AKAHANE ,  Teruo Kaganoi ,  Tetsuya Nagata

IPC分类号： H04L12/26

CPC分类号： H04L43/00 ,  H04L41/0677 ,  H04L43/10 ,  H04L43/50 ,  H04L45/28 ,  H04L49/555 ,  H04L49/557

摘要： A network system comprises a first communication device being set up with a first address; and a second communication device connected with the first communication device via a network and being set up with a second address, wherein the first communication device includes a monitor frame transmitter configured to generate a monitor frame including the second address as a destination address and the first address as a source address, and to output the generated monitor frame to the network; and a monitoring-response frame monitor configured to monitor reception of a monitoring-response frame sent back from the second communication device, wherein the second communication device includes: a monitoring-response frame transmitter configured to, in response to reception of the monitor frame, generate the monitoring-response frame by exchanging the destination address in the received monitor frame for a source address and the source address in the received monitor frame for a destination address, and output the generated monitoring-response frame to the network.

摘要翻译： 网络系统包括：第一通信设备，其具有第一地址; 以及第二通信设备，其经由网络与所述第一通信设备连接并且被建立为具有第二地址，其中所述第一通信设备包括监视帧发送器，所述监视帧发送器被配置为生成包括所述第二地址作为目的地地址的监视帧， 地址作为源地址，并将生成的监视帧输出到网络; 以及监视响应帧监视器，被配置为监视从所述第二通信设备发回的监视响应帧的接收，其中所述第二通信设备包括：监视响应帧发送器，被配置为响应于所述监视帧的接收， 通过在接收到的监视帧中交换目的地址的源地址和接收到的监视帧中的源地址来生成监视响应帧，并将生成的监视响应帧输出到网络。

公开(公告)号：US06513078B1

公开(公告)日：2003-01-28

申请号：US09181167

申请日：1998-10-28

申请人： Teruo Kaganoi ,  Toshiyuki Kanoh

发明人： Teruo Kaganoi ,  Toshiyuki Kanoh

IPC分类号： G06F1300

CPC分类号： G06F13/4018

摘要： Data transfer mode between a plurality of circuit mod modules connected to a data bus is dynamically switched between a time division, space-division multiplexing and so forth for improving data transfer efficiency. For example, the data bus of 4n bit width is used as two data bus of 2n bit width in certain period (transfer mode “b”), as one data bus of 4n bit width in a certain period (transfer mode “a”), and further as four data bus of n bit width in a further certain period (transfer mode “c”). A command of switching of the transfer mode is performed by a transfer control circuit common to respective circuit modules. In response to command of the transfer mode, switching of the bit width of data and switching of the bus connecting condition are performed by the bus adapter circuit.

摘要翻译： 连接到数据总线的多个电路模块模块之间的数据传输模式在时分，空分复用等之间动态切换，以提高数据传输效率。 例如，在一定周期（传输模式“a”）中，将4n位宽的数据总线用作2n位宽的两个数据总线（传输模式“b”），作为4n位宽的一个数据总线， 并且还在另一个特定时段（传输模式“c”）中作为n位宽的四个数据总线。 转移模式的切换命令由各个电路模块共同的转移控制电路来执行。 响应于传送模式的命令，数据的位宽切换和总线连接状态的切换由总线适配器电路执行。

公开(公告)号：US06425048B1

公开(公告)日：2002-07-23

申请号：US09472038

申请日：1999-12-27

申请人： Teruo Kaganoi

发明人： Teruo Kaganoi

IPC分类号： G06F1214

CPC分类号： G06F9/5016 ,  G06F12/023

摘要： A memory pool control circuit according to the invention is provided with a CAM (content addressable memory: associative memory) 11. It further has a monitoring module 12, an area unlocking module 13, a local accessing module 14, an area locking module 15, a search control machine 16, and a timer 17. A plurality of tasks (processes) are operating on a processor 18, and one memory 19 is commonly used by the plurality of tasks (processes). When a task (process) has secured a memory space (called a block here), free areas therein are managed by a group of pointers. A block is divided into a plurality of fixed length fields. A group of flags match the memory space (block) in one-to-one correspondence. The flag group indicate whether or not individual fields are being used, i.e. the flag group indicates whether each individual field is being used or unused (free).

摘要翻译： 根据本发明的存储器池控制电路设置有CAM（内容可寻址存储器：关联存储器）11.它还具有监视模块12，区域解锁模块13，本地访问模块14，区域锁定模块15， 搜索控制机器16和定时器17.多个任务（处理）在处理器18上操作，并且一个存储器19通常由多个任务（处理）使用。 当任务（进程）已经确保了存储空间（在此称为块）时，其中的空闲区域由一组指针管理。 块被分成多个固定长度的场。 一组标志以一对一的对应方式与内存空间（块）匹配。 标志组指示是否正在使用单个字段，即标志组指示是否正在使用或未使用（空闲）各个字段。

公开(公告)号：US6108747A

公开(公告)日：2000-08-22

申请号：US060982

申请日：1998-04-15

申请人： Teruo Kaganoi

发明人： Teruo Kaganoi

IPC分类号： G11C15/04 ,  G06F17/30 ,  G06F12/00

CPC分类号： G06F17/30982

摘要： To provide a method of searching a CAM which enables to search an address of matching contents cyclically recorded in a memory array of the CAM with a priority at once, the method of searching a CAM array (2) having first address lines (20), whereof certain are made active when the CAM array (2) is searched with a search key, comprises steps of: obtaining restricted search results by making address lines of the first address lines (20) having addresses lower than a restriction address inactive; selecting logic of third address lines (70) from logic of the restricted search results when any of the restricted search results is active, and from logic of the first address lines (20) as it is, when none of the restricted search results is active; and outputting a searched address by encoding a lowest active address line of the third address lines (70).

摘要翻译： 为了提供一种搜索CAM的方法，其能够一次性地优先搜索循环记录在CAM的存储器阵列中的匹配内容的地址，搜索具有第一地址线（20）的CAM阵列（2）的方法， 当使用搜索关键字搜索CAM阵列（2）时，某些确定被激活，包括以下步骤：通过使地址低于限制地址的地址行的第一地址行（20）的地址线无效来获得受限搜索结果; 当受限搜索结果为活动时，从受限搜索结果的逻辑中选择第三地址线（70）的逻辑，并且从第一地址线（20）的逻辑开始，当没有受限搜索结果是活动的时候， ; 以及通过对所述第三地址线（70）的最低有效地址线进行编码来输出搜索到的地址。

公开(公告)号：US6026450A

公开(公告)日：2000-02-15

申请号：US917723

申请日：1997-08-27

申请人： Teruo Kaganoi ,  Akio Harasawa

发明人： Teruo Kaganoi ,  Akio Harasawa

IPC分类号： G06F13/28 ,  G06F13/16 ,  G06F13/14

CPC分类号： G06F13/1668

摘要： A transfer control table contains a source memory designation field, a desired region designation field, a shifting amount designation field, and a destination memory designation field. An source selection circuit selects source designation word data from the source word data stored in the source memory according to source memory designation data contained in the source memory designation field to provide the source designation word data. A transfer data bit operation circuit extracts, in response to the source designation word data, only the word data required for transfer as valid word data according to desired region designation data contained in the desired region designation field to shift the valid word data by a bit width that is predetermined based on shifting amount designation data contained in the shifting amount designation field and then to provide the shifted valid word data. A destination selection circuit selects which designation region in the destination memory the shifted valid word data are to be stored in and then provides the shifted valid word data to the designated area in the destination memory.

摘要翻译： 传输控制表包含源存储器指定字段，期望区域指定字段，移位量指定字段和目的地存储器指定字段。 源选择电路根据源存储器指定字段中包含的源存储器指定数据，从存储在源存储器中的源字数据中选择源指定字数据，以提供源指定字数据。 转移数据位运算电路响应于源指定字数据，仅根据包含在期望区域指定字段中的期望区域指定数据，提取作为有效字数据传送所需的字数据，以将有效字数据移位一位 宽度是根据包含在移动量指定字段中的移动量指定数据预先确定的，然后提供移位的有效字数据。 目的地选择电路选择目的地存储器中的哪个指定区域将移位的有效字数据存储在其中，然后将移位的有效字数据提供给目的地存储器中的指定区域。

公开(公告)号：US08437349B2

公开(公告)日：2013-05-07

申请号：US12628455

申请日：2009-12-01

申请人： Teruo Kaganoi ,  Naoya Kumita

发明人： Teruo Kaganoi ,  Naoya Kumita

IPC分类号： H04L12/56

CPC分类号： H04L12/185 ,  H04L12/462 ,  H04L12/4625 ,  H04L12/4633 ,  H04L12/4641

摘要： A network system includes: a core switch; and an edge switch. The edge switch includes: a join message identification unit; and a marking unit. The join message identification unit identifies a join message from among MAC frames from the user network. The marking unit marks mark information to a header of a MAC-in-MAC frame in which the identified join message is encapsulated. The core switch includes: a plurality of input/output ports; a mark identification unit; and a port setup unit. The mark identification unit identifies a MAC-in-MAC frame in which a header is marked with the mark information. The port setup unit associates a multicast group of a join message which is encapsulated in the identified MAC-in-MAC frame, with an input/output port to which the identified MAC-in-MAC frame is input.

摘要翻译： 网络系统包括：核心交换机; 和边缘开关。 边缘切换器包括：加入消息识别单元; 和标记单元。 加入消息识别单元从用户网络识别来自MAC帧的加入消息。 标记单元将标记信息标记到其中封装了所标识的加入消息的MAC-in-MAC帧的报头。 核心交换机包括：多个输入/输出端口; 标记识别单元; 和端口设置单元。 标记识别单元识别标题信息中标有标题的MAC-in-MAC帧。 端口设置单元将封装在所识别的MAC-in-MAC帧中的加入消息的多播组与所输入的MAC-in-MAC帧的输入/输出端口相关联。