公开(公告)号：US20100124141A1

公开(公告)日：2010-05-20

申请号：US12620276

申请日：2009-11-17

Applicant: Tetsuya ARAI

Inventor： Tetsuya ARAI

IPC: G11C8/16

CPC classification number: G11C8/16

Abstract: To provide a plurality of DRAM cells, a plurality of sense amplifiers connected to corresponding bit line pairs, a first column switch and a second column switch assigned to each of the sense amplifiers, data lines connected via the column switches to the sense amplifiers, a first port PORT1 and a second port PORT2 that can input/output write data and read data, and an input/output circuit that connects the PORT1 and the PORT2 to the data lines. Thus, a pseudo dual-port memory can be configured by using an ordinary DRAM array.

Abstract translation: 为了提供多个DRAM单元，连接到对应的位线对的多个读出放大器，分配给每个读出放大器的第一列开关和第二列开关，经由列开关连接到读出放大器的数据线， 第一端口PORT1和可以输入/输出写入数据和读取数据的第二个端口PORT2，以及将PORT1和PORT2连接到数据线的输入/输出电路。 因此，可以通过使用普通DRAM阵列来配置伪双端口存储器。

公开(公告)号：US20100125774A1

公开(公告)日：2010-05-20

申请号：US12620285

申请日：2009-11-17

Applicant: Tetsuya ARAI

Inventor： Tetsuya ARAI

IPC: G06F11/07 ,  G06F12/00

CPC classification number: G06F11/10 ,  G06F11/1048

Abstract: To provide a memory array for information bit that stores information bits, a memory array for check bit that stores check bits, a correction circuit that, in response to a write request, reads the information bit and the check bit corresponding to a write address from the respective memory arrays and corrects an error included in the information bit, and a mixer temporarily holding information bit corrected by the correction circuit. The mixer overwrites only a part of bytes of the held information bits with write data according to a byte mask signal. Accordingly, a capacity required for the memory array for check bit can be reduced while the byte mask function is maintained.

Abstract translation: 为了提供用于存储信息位的信息位的存储器阵列，用于存储校验位的校验位的存储器阵列，响应于写入请求读取与写入地址对应的信息位和校验位的校正电路， 相应的存储器阵列并校​​正包括在信息位中的错误，以及临时保持由校正电路校正的信息位的混合器。 混合器根据字节掩码信号，用写入数据仅覆盖保持的信息位的一部分字节。 因此，在保持字节掩码功能的同时，可以减少用于校验位的存储器阵列所需的容量。

公开(公告)号：US20120161341A1

公开(公告)日：2012-06-28

申请号：US13313552

申请日：2011-12-07

Applicant: Tetsuya ARAI

Inventor： Tetsuya ARAI

IPC: F02M1/10 ,  F02M9/08 ,  F02M1/04

CPC classification number: F02M1/10 ,  F02D9/1025 ,  F02D41/067 ,  F02D2009/0247 ,  F02D2009/0249

Abstract: An automatic choke apparatus for a carburetor includes an electric actuator, a choke valve opening/closing mechanism configured to open and close a choke valve by being driven by a power exerted by the electric actuator, and a controller configured to control operation of the electric actuator. The controller, to which a battery supplies electric power, operates the electric actuator and the choke valve opening/closing mechanism in order that, when the engine is stopped, the choke valve is set in a semi-opened position and, when the engine starts to be cranked, the choke valve is set in a fully-closed position. Accordingly, it is possible to prevent the choke valve from freezing up in the fully-closed state in a case where the engine is stopped under an extremely low temperature environment.

Abstract translation: 一种用于化油器的自动阻风门装置，包括电致动器，阻塞阀开/关机构，其构造成通过由电致动器施加的功率驱动来打开和关闭阻塞阀;以及控制器，被配置为控制电致动器的操作 。 电池提供电力的控制器操作电动执行机构和阻风门开/关机构，以便当发动机停止时，阻流阀设置在半开启位置，并且当发动机起动时 要被起动，阻风门被设置在完全关闭的位置。 因此，在发动机在极低温环境下停止的情况下，可以防止阻塞阀在全闭状态下结冰。

公开(公告)号：US20100182857A1

公开(公告)日：2010-07-22

申请号：US12689696

申请日：2010-01-19

Applicant: Tetsuya ARAI ,  Toshio TSUCHIDA

Inventor： Tetsuya ARAI ,  Toshio TSUCHIDA

IPC: G11C7/00 ,  G11C29/00 ,  G11C8/18

CPC classification number: G11C29/56 ,  G11C29/56012

Abstract: An apparatus testing a semiconductor device may include, but is not limited to, a first strobe signal generating circuit and a detecting circuit. The first strobe signal generating circuit generates a first strobe signal in response to a reference clock supplied from the semiconductor device. The detecting circuit detects a data signal, supplied from the semiconductor device, based on the first strobe signal.

Abstract translation: 测试半导体器件的装置可以包括但不限于第一选通信号发生电路和检测电路。 第一选通信号产生电路响应于从半导体器件提供的参考时钟产生第一选通信号。 检测电路根据第一选通信号检测从半导体装置提供的数据信号。

公开(公告)号：US20100124090A1

公开(公告)日：2010-05-20

申请号：US12620771

申请日：2009-11-18

Applicant: Tetsuya ARAI

Inventor： Tetsuya ARAI

IPC: G11C11/00 ,  G11C5/02

CPC classification number: G11C13/0023 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2207/002 ,  G11C2213/79

Abstract: To provide data lines connected via column switches to a plurality of sense amplifiers and an input/output circuit that, in response to a write request, supplies pre-write data through the data line to selected phase change memory cells and then write data through the data line to the selected phase change memory cells. Thus, a pre-write operation and an actual write operation according to the write data can be performed at high speed. Because only the memory cells selected by a column address are subject to write, consumption power is reduced and lives of the memory cells are not shortened.

Abstract translation: 为了提供通过列开关连接到多个读出放大器的数据线和输入/输出电路，其响应于写请求，通过数据线将预写数据提供给选定的相变存储器单元，然后通过 数据线到选定的相变存储单元。 因此，可以高速执行根据写入数据的预写操作和实际写入操作。 由于只有由列地址选择的存储单元才能进行写入，所以消耗功率降低，存储单元的寿命不会缩短。

公开(公告)号：US20110292710A1

公开(公告)日：2011-12-01

申请号：US13114710

申请日：2011-05-24

Applicant: Koji MATSUBAYASHI ,  Tetsuya ARAI

Inventor： Koji MATSUBAYASHI ,  Tetsuya ARAI

IPC: G11C17/00

CPC classification number: G11C11/406 ,  G11C2211/4065

Abstract: A semiconductor device includes a first and a second ROMs; and a first control circuit having an input node and sets a first and a second addresses that are different each other to be respectively recorded in the first and second ROMs from a plurality of input addresses supplied sequentially into the input node, on the basis of a setting signal, the plurality of input addresses including the first and second addresses, wherein the first control circuit being configured to set an input address as the first address based on the setting signal, and the first control circuit further being configured to set an input address as the second address on the basis of the setting signal when the first and second addresses are different each other in a predetermined portion of bits after the first address is set to the first ROM.

Abstract translation: 半导体器件包括第一和第二ROM; 以及第一控制电路，具有输入节点，并且基于一个输入节点设置彼此不同的第一和第二地址，以分别从依次提供给输入节点的多个输入地址记录在第一和第二ROM中 设置信号，所述多个输入地址包括所述第一和第二地址，其中所述第一控制电路被配置为基于所述设置信号将输入地址设置为所述第一地址，并且所述第一控制电路还被配置为设置输入地址 在第一地址被设置到第一ROM之后，当第一和第二地址在比特的预定部分中彼此不同时，基于设置信号作为第二地址。

公开(公告)号：US20100110803A1

公开(公告)日：2010-05-06

申请号：US12614129

申请日：2009-11-06

Applicant: Tetsuya ARAI

Inventor： Tetsuya ARAI

IPC: G11C7/10 ,  G11C7/06

CPC classification number: G11C7/1006 ,  G11C7/1048 ,  G11C2207/002

Abstract: To provide an input/output circuit that includes a write path to which write data is supplied and a read path to which read data is supplied and first and second data lines that connect the input/output circuit to a memory cell array. The input/output circuit includes a write buffer that supplies the write data on the write path to the first data line, a read amplifier that supplies the read data supplied to the read path through the second data line, and a bypass circuit that supplies the write data on the write path to the read path in response to detection of matching between a write address and a read address. Thus, data collisions can be avoided.

Abstract translation: 提供一种输入/输出电路，其包括写入数据被提供的写入路径和读取数据被提供给的读取路径以及将输入/输出电路连接到存储单元阵列的第一和第二数据线。 输入/输出电路包括写入缓冲器，该写入缓冲器将写入路径上的写入数据提供给第一数据线;读取放大器，提供通过第二数据线提供给读取路径的读取数据;以及旁路电路， 响应于检测到写地址和读地址之间的匹配，将写入路径上的数据写入读路径。 因此，可以避免数据冲突。