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    Nonvolatile semiconductor memory including a controller for providing an improved reprogram operation
    2.
    发明授权
    Nonvolatile semiconductor memory including a controller for providing an improved reprogram operation 有权
    非易失性半导体存储器包括用于提供改进的重新编程操作的控制器

    公开(公告)号：US06333871B1

    公开(公告)日：2001-12-25

    申请号：US09539634

    申请日：2000-03-30

    申请人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    发明人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    IPC分类号： G11C1604

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3463 ,  G11C2211/5642

    摘要： Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.

    摘要翻译： 外部提供的程序数据被锁存到数据锁存电路DLL和DLR中。 在执行多个编程操作的每一次时，判定所锁存的程序数据是否对应于多级的任何阈值。 与判断结果相对应的程序控制信息被锁存在读出锁存电路SL中。 基于锁存的程序控制信息，以逐步的方式执行用于将具有多级的阈值电压设置到存储器单元的编程操作。 即使编程操作结束，外部提供的程序数据也留在数据锁存电路中。 即使由于过度编程条件而重试存储器单元的编程操作，也不再需要再次从外部设备接收程序数据。

    Non-volatile memory device
    4.
    发明授权
    Non-volatile memory device 有权
    非易失性存储器件

    公开(公告)号：US06504764B2

    公开(公告)日：2003-01-07

    申请号：US09985116

    申请日：2001-11-01

    申请人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    发明人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    IPC分类号： G11C1604

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3463 ,  G11C2211/5642

    摘要： A non-volatile memory device having a plurality of memory cells and a control circuit. The control circuit receives operation commands from outside the device and controls the operation of the device according to the commands. The commands include read commands and write commands. In a read command, the control circuit reads data in the memory cells and outputs it. In a write command, the control circuit controls the inputting of data to data latch circuits and then to memory cells. The control circuit provides status information indicating whether the writing of data is a success or a failure.

    摘要翻译： 具有多个存储单元和控制电路的非易失性存储器件。 控制电路从设备外部接收操作命令，并根据命令控制设备的操作。 命令包括读命令和写命令。 在读命令中，控制电路读取存储单元中的数据并将其输出。 在写入命令中，控制电路控制数据到数据锁存电路的输入，然后控制到存储单元。 控制电路提供指示数据写入是成功还是失败的状态信息。

    Non-volatile memory device
    5.
    发明授权
    Non-volatile memory device 有权
    非易失性存储器件

    公开(公告)号：US06320793B2

    公开(公告)日：2001-11-20

    申请号：US09820906

    申请日：2001-03-30

    申请人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    发明人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    IPC分类号： G11C1604

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3463 ,  G11C2211/5642

    摘要： A non-volatile memory device having a plurality of memory cells and a control circuit. The control circuit receives operation commands from outside the device and controls the operation of the device according to the commands. The commands include read commands and write commands. In the read command the control circuit reads data in the memory cells and outputs it. In a write command the control circuit controls the inputting of data to data latch circuits and then to memory cells. The control circuit provides status information indicating whether the writing of data is a success or a failure.

    摘要翻译： 具有多个存储单元和控制电路的非易失性存储器件。 控制电路从设备外部接收操作命令，并根据命令控制设备的操作。 命令包括读命令和写命令。 在读命令中，控制电路读取存储单元中的数据并将其输出。 在写命令中，控制电路控制数据到数据锁存电路的输入，然后控制到存储单元。 控制电路提供指示数据写入是成功还是失败的状态信息。

    Non-volatile memory system including a control device to control writing, reading and storage and output operations of non-volatile devices including memory cells and data latches
    7.
    发明授权
    Non-volatile memory system including a control device to control writing, reading and storage and output operations of non-volatile devices including memory cells and data latches 有权
    非易失性存储器系统，包括用于控制包括存储器单元和数据锁存器的非易失性器件的写入，读取和存储和输出操作的控制装置

    公开(公告)号：US06721207B2

    公开(公告)日：2004-04-13

    申请号：US10211342

    申请日：2002-08-05

    申请人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    发明人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    IPC分类号： G51C1604

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3463 ,  G11C2211/5642

    摘要： A non-volatile memory system is provided with a control device and non-volatile memory devices, each including memory cells and data latches. The control device supplies commands to the non-volatile memory devices, including a write command, and first and second read commands. When the control device supplies the write command with write address information and data for storing in the non-volatile memory device, it stores the data to the data latches and then to the memory cells, and then verifies storage. When the control device supplies the first read command with read address information, the nonvolatile memory device reads data stored in the memory cells to the data latches and then outputs the data in the data latches to the control device. When the control device supplies the second read command, the non-volatile memory device outputs data in the data latches to the control device.

    摘要翻译： 非易失性存储器系统设置有控制设备和非易失性存储器设备，每个包括存储器单元和数据锁存器。 控制装置向非易失性存储装置提供包括写入命令以及第一和第二读取命令的命令。 当控制装置向写入命令提供写入地址信息和用于存储在非易失性存储器件中的数据时，它将数据存储到数据锁存器，然后存储到存储器单元，然后验证存储器。 当控制装置向读取地址信息提供第一读取命令时，非易失性存储器件将存储在存储器单元中的数据读取到数据锁存器，然后将数据锁存器中的数据输出到控制装置。 当控制装置提供第二读取命令时，非易失性存储装置将数据锁存器中的数据输出到控制装置。

    Nonvolatile memory system
    8.
    发明授权
    Nonvolatile memory system 有权
    非易失性存储器系统

    公开(公告)号：US06507520B2

    公开(公告)日：2003-01-14

    申请号：US10011723

    申请日：2001-12-11

    申请人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    发明人： Tetsuya Tsujikawa ,  Atsushi Nozoe ,  Michitaro Kanamitsu ,  Shoji Kubono ,  Eiji Yamamoto ,  Ken Matsubara

    IPC分类号： G11C1604

    CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3463 ,  G11C2211/5642

    摘要： Externally supplied program data is latched into data latch circuits DLL and DLR. A judgment is made as to whether or not the latched program data corresponds to any threshold value of multi-levels every time each of plural programing operations is carried out. The program control information corresponding to the judgment result is latched into a sense latch circuit SL. Based upon the latched program control information, the programing operation for setting threshold voltages having multi-levels to a memory cell is carried out in a stepwise manner. Even when the programing operation is ended, the externally supplied program data is left in the data latch circuit. Even when the programing operation of the memory cell is retried due to the overprograming condition, the program data is no longer required to be again received from the external device.

    摘要翻译： 外部提供的程序数据被锁存在数据锁存电路DLL和DLR中。 在执行多个编程操作的每一次时，判定所锁存的程序数据是否对应于多级的任何阈值。 与判断结果相对应的程序控制信息被锁存在读出锁存电路SL中。 基于锁存的程序控制信息，以逐步的方式执行用于将具有多级的阈值电压设置到存储器单元的编程操作。 即使编程操作结束，外部提供的程序数据也留在数据锁存电路中。 即使由于过度编程条件而重试存储器单元的编程操作，也不再需要再次从外部设备接收程序数据。