公开(公告)号：US09905428B2

公开(公告)日：2018-02-27

申请号：US14930633

申请日：2015-11-02

Applicant: Texas Instruments Incorporated

Inventor： Andrew D Strachan ,  Alexei Sadovnikov ,  Christopher Boguslaw Kocon

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/66 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L21/28114 ,  H01L21/28158 ,  H01L29/0634 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7831 ,  H01L29/7835

Abstract: A semiconductor device includes a split-gate lateral extended drain MOS transistor, which includes a first gate and a second gate laterally adjacent to the first gate. The first gate is laterally separated from the second gate by a gap of 10 nanometers to 250 nanometers. The first gate extends at least partially over the body, and the second gate extends at least partially over a drain drift region. The drain drift region abuts the body at a top surface of the substrate. A boundary between the drain drift region and the body at the top surface of the substrate is located under at least one of the first gate, the second gate and the gap between the first gate and the second gate. The second gate may be coupled to a gate bias voltage node or a gate signal node.

公开(公告)号：US09773777B2

公开(公告)日：2017-09-26

申请号：US14991881

申请日：2016-01-08

Applicant: Texas Instruments Incorporated

Inventor： Andrew D Strachan ,  Alexei Sadovnikov ,  Gang Xue ,  Dening Wang

IPC: H01L27/02 ,  H01L29/66 ,  H01L29/861 ,  H01L29/06

CPC classification number: H01L27/0255 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/6609 ,  H01L29/66113 ,  H01L29/861 ,  H01L29/8618

Abstract: A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 1×1017 cm−3, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.