公开(公告)号：US09743530B2

公开(公告)日：2017-08-22

申请号：US14798538

申请日：2015-07-14

Applicant: Texas Instruments Incorporated

Inventor： Chikara Azuma

IPC: H05K1/18 ,  H05K3/30 ,  H01G2/06 ,  H01G4/06 ,  H01G4/30 ,  H01L23/498 ,  H01L23/50 ,  H05K1/02 ,  H05K1/16 ,  H05K3/42 ,  H01L23/00 ,  H05K3/46

CPC classification number: H05K3/303 ,  H01G2/065 ,  H01G4/06 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/30105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/181 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10643 ,  H05K2201/10674 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A plurality of electrically conductive material layers and a plurality of dielectric layers are alternately stacked on a second substrate. The plurality of electrically conductive material layers comprise first and second patterns. The first pattern comprises at least a first pair of overlaying areas free of the electrically conductive material, and the second pattern comprises at least a second pair of overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. The plurality of electrically conductive material layers are electrically isolated from one another by the dielectric layers.

公开(公告)号：US20160007481A1

公开(公告)日：2016-01-07

申请号：US14798538

申请日：2015-07-14

Applicant: Texas Instruments Incorporated

Inventor： Chikara Azuma

IPC: H05K3/30 ,  H05K3/46 ,  H05K3/42

CPC classification number: H05K3/303 ,  H01G2/065 ,  H01G4/06 ,  H01G4/30 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19106 ,  H01L2924/30105 ,  H05K1/0231 ,  H05K1/162 ,  H05K1/181 ,  H05K1/185 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0187 ,  H05K2201/10643 ,  H05K2201/10674 ,  Y10T29/4913 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method of assembling a packaged semiconductor device starts by dropping a pre-formed capacitor precursor on a surface of or within a first substrate. An integrated circuit die is dropped on either of the first substrate. If the pre-formed capacitor precursor lacks at least a first pair of vias for providing an electrical contact between capacitor plates of said chip capacitor, then at least a first pair of vias is formed in said pre-formed capacitor precursor. The first pair of vias are filled with an electrically conductive material to form the chip capacitor, wherein said filling of said vias provides an electrical contact between said first and second capacitor plates of said chip capacitor and said electrically conductive contact regions on said first substrate. A plurality of electrically conductive material layers and a plurality of dielectric layers are alternately stacked on a second substrate. The plurality of electrically conductive material layers comprise first and second patterns. The first pattern comprises at least a first pair of overlaying areas free of said electrically conductive material, and said second pattern comprises at least a second pair of overlaying areas free of said electrically conductive material. The first pair of areas overlay areas of the second pattern having said electrically conductive material and the second pair of areas overlay areas of the first pattern having said electrically conductive material. The plurality of electrically conductive material layers are electrically isolated from one another by the dielectric layers.

Abstract translation: 组装封装的半导体器件的方法是通过在第一衬底的表面上或在第一衬底的表面上放置预先形成的电容器前体开始的。 集成电路管芯掉在第一衬底中的任一个上。 如果预先形成的电容器前体缺少至少第一对通孔，用于提供所述片状电容器的电容器板之间的电接触，则在所述预形成电容器前体中形成至少第一对通孔。 第一对通孔填充有导电材料以形成片状电容器，其中所述通孔的所述填充提供所述片状电容器的所述第一和第二电容器板与所述第一衬底上的所述导电接触区域之间的电接触。 多个导电材料层和多个电介质层交替堆叠在第二基板上。 多个导电材料层包括第一和第二图案。 第一图案包括至少第一对没有所述导电材料的重叠区域，并且所述第二图案包括至少一个没有导电材料的第二对覆盖区域。 第一对区域覆盖具有所述导电材料的第二图案的区域，并且第二对区域覆盖具有所述导电材料的第一图案的区域。 多个导电材料层通过电介质层彼此电隔离。