公开(公告)号：US12080755B2

公开(公告)日：2024-09-03

申请号：US17512484

申请日：2021-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Furen Lin ,  Yunlong Liu ,  Zhi Peng Feng ,  Rui Liu ,  Rui Song ,  Manoj K Jain

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/495 ,  H01L27/08 ,  H01L29/66 ,  H01L49/02

CPC classification number: H01L28/91 ,  H01L28/92

Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

公开(公告)号：US10746890B2

公开(公告)日：2020-08-18

申请号：US16101867

申请日：2018-08-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Furen Lin ,  Frank Baiocchi ,  Haian Lin ,  Yunlong Liu ,  Lark Liu ,  Wei Song ,  ZiQiang Zhao

IPC: H01L29/417 ,  G01V1/38 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  G01V1/16 ,  G01V1/18 ,  G01V1/24 ,  H01L29/423

Abstract: A method of forming an electronic device includes forming a plurality of closed loops over a semiconductor substrate. Each closed loop has a first and a second polysilicon gate structure joined at first and second ends. Each closed loop includes an inner portion and an end portion. In the inner portion the first polysilicon gate structure runs about parallel to the second polysilicon gate structure. In the outer portion the first polysilicon gate structure converges with the second polysilicon gate structure. The method further includes forming a plurality of trench contacts. Each of the trench contacts is located between a respective pair of closed loops, passes through an epitaxial layer and contacts the substrate. The length of the trench contacts is no greater than the length of the inner portions.

公开(公告)号：US20220416014A1

公开(公告)日：2022-12-29

申请号：US17512484

申请日：2021-10-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Furen Lin ,  Yunlong Liu ,  Zhi Peng Feng ,  Rui Liu ,  Rui Song ,  Manoj K. Jain

IPC: H01L49/02

Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

公开(公告)号：US10068977B2

公开(公告)日：2018-09-04

申请号：US15601591

申请日：2017-05-22

Applicant: Texas Instruments Incorporated

Inventor： Furen Lin ,  Frank Baiocchi ,  Haian Lin ,  Yunlong Liu ,  Lark Liu ,  Wei Song ,  ZiQiang Zhao

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/66 ,  H01L27/088

CPC classification number: G01V1/3808 ,  G01V1/166 ,  G01V1/18 ,  G01V1/247 ,  G01V1/38 ,  G01V1/3852 ,  G01V2210/1427 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7823 ,  H01L29/7835 ,  Y10T24/39

Abstract: A power MOSFET IC device including an array of MOSFET cells formed in a semiconductor substrate. The array of MOSFET cells comprises an interior region of interior MOSFET cells and an outer edge region of peripheral MOSFET cells, each interior MOSFET cell of the interior region of the array comprising a pair of interior MOSFET devices coupled to each other at a common drain contact. In an example embodiment, each interior MOSFET device includes a source contact (SCT) trench extended into a substrate contact region of the semiconductor substrate. The SCT trench is provided with a length less than a linear portion of a polysilicon gate of the interior MOSFET device, wherein the SCT trench is aligned to the polysilicon gate having a curvilinear layout geometry.

公开(公告)号：US20240395854A1

公开(公告)日：2024-11-28

申请号：US18795747

申请日：2024-08-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Furen Lin ,  Yunlong Liu ,  Zhi Peng Feng ,  Rui Liu ,  Rui Song ,  Manoj K Jain

IPC: H01G4/30

Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

公开(公告)号：US10707344B2

公开(公告)日：2020-07-07

申请号：US15817488

申请日：2017-11-20

Applicant: Texas Instruments Incorporated

Inventor： Furen Lin ,  Frank Baiocchi ,  Yunlong Liu ,  Lark Liu ,  Tianping Lv ,  Peter Lin ,  Ho Lin

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L21/74 ,  H01L29/06 ,  H01L29/10

Abstract: A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells) including a first cell and at least a second cell each having a gate stack over a body region. A trench has an aspect ratio of >3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) from a source doped a second conductivity type to the substrate. A field plate (FP) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler within. A drain doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.

公开(公告)号：US09853144B2

公开(公告)日：2017-12-26

申请号：US15171136

申请日：2016-06-02

Applicant: Texas Instruments Incorporated

Inventor： Furen Lin ,  Frank Baiocchi ,  Yunlong Liu ,  Lark Liu ,  Tianping Lv ,  Peter Lin ,  Ho Lin

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L21/768 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/402 ,  H01L29/407 ,  H01L29/4175 ,  H01L29/66659 ,  H01L29/66696 ,  H01L29/7835

Abstract: A planar gate power MOSFET includes a substrate having a semiconductor surface doped a first conductivity type, a plurality of transistor cells (cells) including a first cell and at least a second cell each having a gate stack over a body region. A trench has an aspect ratio of >3 extending down from a top side of the semiconductor surface between the gate stacks providing a source contact (SCT) from a source doped a second conductivity type to the substrate. A field plate (FP) is over the gate stacks that provides a liner for the trench. The trench has a refractory metal or platinum-group metal (PGM) metal filler within. A drain doped the second conductivity type is in the semiconductor surface on a side of the gate stacks opposite the trench.