公开(公告)号：US09947783B2

公开(公告)日：2018-04-17

申请号：US15135154

申请日：2016-04-21

Applicant: Texas Instruments Incorporated

Inventor： Chin-Yu Tsai ,  Imran Khan ,  Xiaoju Wu

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L21/761 ,  H01L21/76202 ,  H01L21/76224 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/66681 ,  H01L29/7833

Abstract: A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.

公开(公告)号：US09608109B1

公开(公告)日：2017-03-28

申请号：US15135117

申请日：2016-04-21

Applicant: Texas Instruments Incorporated

Inventor： Chin-Yu Tsai ,  Imran Khan ,  Shaoping Tang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L21/762 ,  H01L29/167 ,  H01L27/06

CPC classification number: H01L21/76202 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7833

Abstract: An n-channel DEMOS device a pwell finger defining a length and a width direction formed within a doped surface layer. A first nwell is on one side of the pwell finger including a source and a second nwell on an opposite side of the pwell finger includes a drain. A gate stack is over a channel region the pwell finger between the source and drain. A field dielectric layer is on the surface layer defining a first active area including a first active area boundary along the width direction (WD boundary) that has the channel region therein. A first p-type layer is outside the first active area at least a first minimum distance from the WD boundary and a second p-type layer is doped less and is closer to the WD boundary than the first minimum distance.

公开(公告)号：US20140183630A1

公开(公告)日：2014-07-03

申请号：US14142006

申请日：2013-12-27

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Amitava Chatterjee ,  Imran Khan

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823456

Abstract: An integrated circuit containing a MOS transistor and a DEMOS transistor of a same polarity may be formed by implanting dopants of a same conductivity type as source/drain regions of the MOS transistor and the DEMOS transistor through a gate of the MOS transistor and through a gate of the DEMOS transistor. The implanted dopants are blocked from a drain-side edge of the DEMOS transistor gate. The implanted dopants form a drain enhancement region under the DEMOS transistor gate in a drift region of an extended drain of the DEMOS transistor.

Abstract translation: 可以通过将MOS晶体管和DEMOS晶体管的源/漏区相同的导电类型的掺杂剂通过MOS晶体管的栅极并通过栅极形成包含具有相同极性的MOS晶体管和DEMOS晶体管的集成电路 的DEMOS晶体管。 注入的掺杂剂从DEMOS晶体管栅极的漏极侧边缘封闭。 注入的掺杂剂在DEMOS晶体管栅极的DEMOS晶体管的扩展漏极的漂移区域内形成漏极增强区域。

公开(公告)号：US08933510B2

公开(公告)日：2015-01-13

申请号：US14142006

申请日：2013-12-27

Applicant: Texas Instruments Incorporated

Inventor： Pinghai Hao ,  Amitava Chatterjee ,  Imran Khan

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L21/823412 ,  H01L21/823418 ,  H01L21/823456

Abstract: An integrated circuit containing a MOS transistor and a DEMOS transistor of a same polarity may be formed by implanting dopants of a same conductivity type as source/drain regions of the MOS transistor and the DEMOS transistor through a gate of the MOS transistor and through a gate of the DEMOS transistor. The implanted dopants are blocked from a drain-side edge of the DEMOS transistor gate. The implanted dopants form a drain enhancement region under the DEMOS transistor gate in a drift region of an extended drain of the DEMOS transistor.

Abstract translation: 可以通过将MOS晶体管和DEMOS晶体管的源/漏区相同的导电类型的掺杂剂通过MOS晶体管的栅极并通过栅极形成包含具有相同极性的MOS晶体管和DEMOS晶体管的集成电路 的DEMOS晶体管。 注入的掺杂剂从DEMOS晶体管栅极的漏极侧边缘封闭。 注入的掺杂剂在DEMOS晶体管栅极的DEMOS晶体管的扩展漏极的漂移区域内形成漏极增强区域。