公开(公告)号：US09608109B1

公开(公告)日：2017-03-28

申请号：US15135117

申请日：2016-04-21

Applicant: Texas Instruments Incorporated

Inventor： Chin-Yu Tsai ,  Imran Khan ,  Shaoping Tang

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L29/66 ,  H01L21/762 ,  H01L29/167 ,  H01L27/06

CPC classification number: H01L21/76202 ,  H01L21/761 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/1087 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7833

Abstract: An n-channel DEMOS device a pwell finger defining a length and a width direction formed within a doped surface layer. A first nwell is on one side of the pwell finger including a source and a second nwell on an opposite side of the pwell finger includes a drain. A gate stack is over a channel region the pwell finger between the source and drain. A field dielectric layer is on the surface layer defining a first active area including a first active area boundary along the width direction (WD boundary) that has the channel region therein. A first p-type layer is outside the first active area at least a first minimum distance from the WD boundary and a second p-type layer is doped less and is closer to the WD boundary than the first minimum distance.

公开(公告)号：US09577094B2

公开(公告)日：2017-02-21

申请号：US14885637

申请日：2015-10-16

Applicant: Texas Instruments Incorporated

Inventor： Shaoping Tang ,  Amitava Chatterjee ,  Imran Mahmood Khan ,  Kaiping Liu

IPC: H01L29/08 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/265 ,  H01L21/3213 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/06 ,  H01L21/28 ,  H01L29/49 ,  H01L29/10

CPC classification number: H01L29/7836 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28105 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823892 ,  H01L27/0617 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

Abstract translation: 集成电路和方法包括具有改进的CHC可靠性的DEMOS晶体管，其在DEMOS栅极下具有较低电阻表面沟道，其转变到DEMOS晶体管栅极的漏极边缘下方的较低电阻的地下通道。

公开(公告)号：US09202912B2

公开(公告)日：2015-12-01

申请号：US14576693

申请日：2014-12-19

Applicant: Texas Instruments Incorporated

Inventor： Shaoping Tang ,  Amitava Chatterjee ,  Imran Mahmood Khan ,  Kaiping Liu

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/3213 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/7836 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28105 ,  H01L21/32133 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823892 ,  H01L27/0617 ,  H01L27/0922 ,  H01L27/0928 ,  H01L29/0847 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/4933 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/66537 ,  H01L29/66575 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

Abstract translation: 集成电路和方法包括具有改进的CHC可靠性的DEMOS晶体管，其具有在DEMOS栅极下方的较低电阻表面沟道，其转变到DEMOS晶体管栅极的漏极边缘下方的较低电阻的地下通道。