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公开(公告)号：US20180034453A1
公开(公告)日：2018-02-01
申请号：US15220225
申请日：2016-07-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Kannan Krishna
IPC: H03K5/24
CPC classification number: H03K5/24 , H03K2005/00091
Abstract: A delay compensated comparator circuit is disclosed. The circuit includes an amplifier circuit having a first input terminal coupled to receive a reference signal and having a second input terminal and a first output terminal. A capacitor is arranged to couple an input signal to the second input terminal. A resistor is coupled between the first output terminal and the second input terminal. A comparator circuit has a third input terminal coupled to receive the input signal, a fourth input terminal coupled to the first output terminal, and a second output terminal.
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公开(公告)号：US11463086B2
公开(公告)日：2022-10-04
申请号：US16029277
申请日：2018-07-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Kannan Krishna
IPC: H03K17/687 , H02M7/5387 , H02M3/337 , H02M3/158
Abstract: A circuit comprises an H-bridge circuit that includes a pair of current sources and a plurality of transistors. The H-bridge circuit includes a first output and a second output. One of the current sources is coupled to receive a supply voltage. A control circuit is configured to control, based on a sum of voltages on the first and second outputs, current of at least one of the current sources through at least some of the plurality of transistors.
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公开(公告)号：US20170214396A1
公开(公告)日：2017-07-27
申请号：US15483670
申请日：2017-04-10
Applicant: Texas Instruments Incorporated
Inventor： Kannan Krishna
CPC classification number: H03K5/003 , H03K3/356104 , H03K3/356121 , H03K5/2481
Abstract: A method and device for input offset cancellation utilizing a latched comparator that is configurable as a linear amplifier capable of sampling and cancelling offset in the inputs to the latched comparator. The latched comparator is configured according to three control signals for operation in three operating intervals. During a first operating interval, the latched comparator is configured as a linear amplifier that samples the offset at the inputs to the latched comparator. Based on the sampled offset, the linear amplifier cancels the offset in the inputs to the latched comparator. During a second operating interval, the latched comparator reverts to operation as comparator and the inputs to the latch are reset. During a third interval, the latch resolves the inputs to the comparator and generates an output signal indicating.
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公开(公告)号：US09621145B2
公开(公告)日：2017-04-11
申请号：US15153028
申请日：2016-05-12
Applicant: Texas Instruments Incorporated
Inventor： Kannan Krishna
CPC classification number: H03K5/003 , H03K3/356104 , H03K3/356121 , H03K5/2481
Abstract: A method and device for input offset cancellation utilizing a latched comparator that is configurable as a linear amplifier capable of sampling and cancelling offset in the inputs to the latched comparator. The latched comparator is configured according to three control signals for operation in three operating intervals. During a first operating interval, the latched comparator is configured as a linear amplifier that samples the offset at the inputs to the latched comparator. Based on the sampled offset, the linear amplifier cancels the offset in the inputs to the latched comparator. During a second operating interval, the latched comparator is configured to operate as comparator and the inputs to the latch are reset. During a third interval, the latch resolves the inputs to the comparator and generates an output signal indicating the relative values of the inputs.
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Patent Agency Ranking
公开(公告)号：US09979383B2
公开(公告)日：2018-05-22
申请号：US15220225
申请日：2016-07-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Kannan Krishna
CPC classification number: H03K5/24 , H03K2005/00091
Abstract: A delay compensated comparator circuit is disclosed. The circuit includes an amplifier circuit having a first input terminal coupled to receive a reference signal and having a second input terminal and a first output terminal. A capacitor is arranged to couple an input signal to the second input terminal. A resistor is coupled between the first output terminal and the second input terminal. A comparator circuit has a third input terminal coupled to receive the input signal, a fourth input terminal coupled to the first output terminal, and a second output terminal.
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公开(公告)号：US09973179B2
公开(公告)日：2018-05-15
申请号：US15483670
申请日：2017-04-10
Applicant: Texas Instruments Incorporated
Inventor： Kannan Krishna
CPC classification number: H03K5/003 , H03K3/356104 , H03K3/356121 , H03K5/2481
Abstract: A method and device for input offset cancellation utilizing a latched comparator that is configurable as a linear amplifier capable of sampling and cancelling offset in the inputs to the latched comparator. The latched comparator is configured according to three control signals for operation in three operating intervals. During a first operating interval, the latched comparator is configured as a linear amplifier that samples the offset at the inputs to the latched comparator. Based on the sampled offset, the linear amplifier cancels the offset in the inputs to the latched comparator. During a second operating interval, the latched comparator reverts to operation as comparator and the inputs to the latch are reset. During a third interval, the latch resolves the inputs to the comparator and generates an output signal indicating.
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公开(公告)号：US20160336933A1
公开(公告)日：2016-11-17
申请号：US15153028
申请日：2016-05-12
Applicant: Texas Instruments Incorporated
Inventor： Kannan Krishna
CPC classification number: H03K5/003 , H03K3/356104 , H03K3/356121 , H03K5/2481
Abstract: A method and device for input offset cancellation utilizing a latched comparator that is configurable as a linear amplifier capable of sampling and cancelling offset in the inputs to the latched comparator. The latched comparator is configured according to three control signals for operation in three operating intervals. During a first operating interval, the latched comparator is configured as a linear amplifier that samples the offset at the inputs to the latched comparator. Based on the sampled offset, the linear amplifier cancels the offset in the inputs to the latched comparator. During a second operating interval, the latched comparator is configured to operate as comparator and the inputs to the latch are reset. During a third interval, the latch resolves the inputs to the comparator and generates an output signal indicating the relative values of the inputs.
Abstract translation: 一种用于输入偏移消除的方法和装置，其使用锁存比较器，该锁存比较器可配置为能够对锁存比较器的输入中的采样和抵消偏移的线性放大器。 锁存的比较器根据三个控制信号进行配置，以在三个操作间隔内运行。 在第一操作间隔期间，锁存比较器被配置为线性放大器，其将输入处的偏移量采样到锁存的比较器。 基于采样偏移，线性放大器抵消锁存比较器的输入偏移。 在第二操作间隔期间，锁存比较器被配置为作为比较器操作，并且锁存器的输入被复位。 在第三个间隔期间，锁存器将比较器的输入分解，并产生一个指示输入相对值的输出信号。
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公开(公告)号：US20250141412A1
公开(公告)日：2025-05-01
申请号：US18385848
申请日：2023-10-31
Applicant: Texas Instruments Incorporated
Inventor： Jianquan Liao , Zejian Wang , Pourya Assem , Kannan Krishna , Zhenzhen Chen , Jing Xu , Shurong Xia , Chi Cheong
Abstract: An example apparatus includes: class D amplifier circuitry having a first input, a second input, a third input, and an output, the first input of the class D amplifier circuitry coupled to the output of the class D amplifier circuitry; and class AB amplifier circuitry having a first input, a second input, a third input, and an output, the first input of the class AB amplifier circuitry coupled to the first input of the class D amplifier circuitry and the output of the class D amplifier circuitry, the second and third inputs of the class AB amplifier circuitry coupled to the second and third inputs of the class D amplifier circuitry, and the output of the class AB amplifier circuitry.
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公开(公告)号：US09614517B2
公开(公告)日：2017-04-04
申请号：US14796749
申请日：2015-07-10
Applicant: Texas Instruments Incorporated
Inventor： Kannan Krishna
CPC classification number: H03K17/165 , H03K5/156 , H03K7/08 , H03K17/166
Abstract: An adaptive driver includes a gate driver having at least one driving transistor for driving a control node of switching transistor(s) that includes an output node (OUT) which provides Vout. An adjustable current source is in series with the driving transistor, a high pass filter (HPF) is between OUT and ground for detecting a slew rate of the switching transistor and outputting a voltage pulse (Vslp) output having a peak voltage amplitude at least monotonically reflecting a slope of Vout during switching. Detection signal processing circuitry is coupled to the output of the HPF for processing Vslp and slew rate control circuitry has an input coupled to the output of the detection signal processing circuitry. The output of the slew rate control circuitry is coupled to the current source for controlling its current level for changing the slew rate of the switching transistor to provide a desired slew rate range.
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