公开(公告)号：US20210327525A1

公开(公告)日：2021-10-21

申请号：US17364647

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Lei Wu

IPC: G11C29/16 ,  G11C29/10 ,  G01R31/3185 ,  G11C29/32 ,  G11C29/12 ,  G11C29/26 ,  G11C29/02 ,  G11C29/14 ,  G11C29/36

Abstract: A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.

公开(公告)号：US11087857B2

公开(公告)日：2021-08-10

申请号：US16192796

申请日：2018-11-15

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Lei Wu

IPC: G11C29/16 ,  G11C29/10 ,  G01R31/3185 ,  G11C29/32 ,  G11C29/12 ,  G11C29/26 ,  G11C29/02 ,  G11C29/14 ,  G11C29/36

Abstract: A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.

公开(公告)号：US12243603B2

公开(公告)日：2025-03-04

申请号：US18392740

申请日：2023-12-21

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Lei Wu

IPC: G11C29/12 ,  G01R31/3185 ,  G11C29/02 ,  G11C29/10 ,  G11C29/14 ,  G11C29/16 ,  G11C29/26 ,  G11C29/32 ,  G11C29/36

Abstract: Methods to test functional memory interface logic of a core under test utilize a built-in-self-test (BIST) controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at BIST mode, an at-speed functional mode is utilized to capture a desired memory output.

公开(公告)号：US20190156908A1

公开(公告)日：2019-05-23

申请号：US16192796

申请日：2018-11-15

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Lei Wu

IPC: G11C29/16 ,  G11C29/10 ,  G11C29/12 ,  G11C29/32 ,  G01R31/3185

Abstract: A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.

公开(公告)号：US20240120016A1

公开(公告)日：2024-04-11

申请号：US18392740

申请日：2023-12-21

Applicant: Texas Instruments Incorporated

Inventor： Devanathan Varadarajan ,  Lei Wu

IPC: G11C29/16 ,  G01R31/3185 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12 ,  G11C29/14 ,  G11C29/26 ,  G11C29/32 ,  G11C29/36

CPC classification number: G11C29/16 ,  G01R31/318594 ,  G01R31/318597 ,  G11C29/022 ,  G11C29/023 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/26 ,  G11C29/32 ,  G11C29/36

Abstract: Methods to test functional memory interface logic of a core under test utilize a built-in-self-test (BIST) controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at BIST mode, an at-speed functional mode is utilized to capture a desired memory output.