公开(公告)号：US09093315B2

公开(公告)日：2015-07-28

申请号：US14099973

申请日：2013-12-08

Applicant: Texas Instruments Incorporated

Inventor： Shaofeng Yu ,  Russell Carlton McMullan ,  Wah Kit Loh

IPC: H01L29/08 ,  H01L27/11 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0847

Abstract: An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.

Abstract translation: 包含SAR SRAM和CMOS逻辑的集成电路，其中SAR SRAM单元的栅极延伸上的侧壁间隔物比逻辑PMOS栅极上的侧壁间隔更薄，使得漏极节点SRAM PSD层的深度保持在 伸展接触。 形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括选择性地蚀刻在SAR SRAM单元的栅极延伸上的侧壁间隔物，使得漏极节点SRAM PSD层的深度保持在拉伸接触下 。 形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括在漏极节点SRAM PSD层中选择性地注入额外的p型掺杂剂，使得漏极节点SRAM PSD层的深度保持在拉伸接触下。

公开(公告)号：US09123570B2

公开(公告)日：2015-09-01

申请号：US13937398

申请日：2013-07-09

Applicant: Texas Instruments Incorporated

Inventor： Angelo Pinto ,  Frank S. Johnson ,  Benjamin P. McKee ,  Shaofeng Yu

IPC: H01L27/092 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/10 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L27/0928 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/76224 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/1054 ,  H01L29/7833

Abstract: Optimizing carrier mobilities in MOS transistors in CMOS ICs requires forming (100)-oriented silicon regions for NMOS and (110) regions for PMOS. Methods such as amorphization and templated recrystallization (ATR) have disadvantages for fabrication of deep submicron CMOS. This invention is a method of forming an integrated circuit (IC) which has (100) and (110)-oriented regions. The method forms a directly bonded silicon (DSB) layer of (110)-oriented silicon on a (100)-oriented substrate. The DSB layer is removed in the NMOS regions and a (100)-oriented silicon layer is formed by selective epitaxial growth (SEG), using the substrate as the seed layer. NMOS transistors are formed on the SEG layer, while PMOS transistors are formed on the DSB layer. An integrated circuit formed with the inventive method is also disclosed.

Abstract translation: 在CMOS IC中的MOS晶体管中优化载流子迁移率需要为PMOS形成用于NMOS和（110）区域的（100）取向的硅区域。 诸如非晶化和模板重结晶（ATR）的方法具有制造深亚微米CMOS的缺点。 本发明是形成具有（100）和（110）取向区域的​​集成电路（IC）的方法。 该方法在（100）取向的衬底上形成（110）取向的硅的直接键合的硅（DSB）层。 在NMOS区域中去除DSB层，并且使用基底作为种子层，通过选择性外延生长（SEG）形成（100）取向硅层。 在SEG层上形成NMOS晶体管，而在DSB层上形成PMOS晶体管。 还公开了用本发明方法形成的集成电路。

公开(公告)号：US20140346609A1

公开(公告)日：2014-11-27

申请号：US14099973

申请日：2013-12-08

Applicant: Texas Instruments Incorporated

Inventor： Shaofeng Yu ,  Russell Carlton McMullan ,  Wah Kit Loh

IPC: H01L27/11 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L27/1104 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0847

Abstract: An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.

Abstract translation: 包含SAR SRAM和CMOS逻辑的集成电路，其中SAR SRAM单元的栅极延伸上的侧壁间隔物比逻辑PMOS栅极上的侧壁间隔更薄，使得漏极节点SRAM PSD层的深度保持在 伸展接触。 形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括选择性地蚀刻在SAR SRAM单元的栅极延伸上的侧壁间隔物，使得漏极节点SRAM PSD层的深度保持在拉伸接触下 。 形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括在漏极节点SRAM PSD层中选择性地注入额外的p型掺杂剂，使得漏极节点SRAM PSD层的深度保持在拉伸接触下。

公开(公告)号：US09412869B2

公开(公告)日：2016-08-09

申请号：US14559451

申请日：2014-12-03

Applicant: Texas Instruments Incorporated

Inventor： Samuel Zafar Nawaz ,  Shaofeng Yu ,  Jeffrey E. Brighton ,  Song Zhao

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7835

Abstract: An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.