公开(公告)号：US09412869B2

公开(公告)日：2016-08-09

申请号：US14559451

申请日：2014-12-03

Applicant: Texas Instruments Incorporated

Inventor： Samuel Zafar Nawaz ,  Shaofeng Yu ,  Jeffrey E. Brighton ,  Song Zhao

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7835

Abstract: An integrated circuit contains a transistor with a stress enhancement region on the source side only. In a DeMOS transistor, forming the stress enhancement region on the source side only and not forming a stress enhancement region in the drain extension increases the resistance of the drain extension region enabling formation of a DeMOS transistor with reduced area. In a MOS transistor, by forming the stress enhancement region on the source side only and eliminating the stress enhancement region from the drain side, transistor leakage is reduced and CHC reliability improved.

公开(公告)号：US09543374B2

公开(公告)日：2017-01-10

申请号：US14569975

申请日：2014-12-15

Applicant: Texas Instruments Incorporated

Inventor： Greg Charles Baldwin ,  Kamel Benaissa ,  Sarah Liu ,  Song Zhao

IPC: G06F17/50 ,  H01L49/02 ,  H01L27/06 ,  H01L21/265 ,  H01L21/8238 ,  H02J7/02 ,  H02J7/00

CPC classification number: H01L28/22 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/0629 ,  H02J7/0044 ,  H02J7/025

Abstract: A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow.

Abstract translation: 一种将低TCR电阻添加到基准CMOS制造流程的方法。 在CMOS制造流程中形成低TCR电阻器的方法。 在CMOS制造流程中形成具有低TCR电阻器的n型和p型晶体管的方法。

公开(公告)号：US20160172443A1

公开(公告)日：2016-06-16

申请号：US14967199

申请日：2015-12-11

Applicant: Texas Instruments Incorporated

Inventor： Younsung Choi ,  Kwan-Yong Lim ,  Seung-Chul Song ,  Song Zhao

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/0847 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28035 ,  H01L29/4916 ,  H01L29/66575 ,  H01L29/78

Abstract: A method for tuning a threshold voltage of a semiconductor device includes implanting at least one dopant in a semiconductor substrate at an angle to form a source region and/or a drain region of a transistor. The angle is oblique to a surface of the substrate. Implanting the at least one dopant at the angle alters a flat-band voltage of the transistor and shifts the threshold voltage of the transistor. The at least one dopant or at least one additional dopant can be implanted in a gate electrical contact of the transistor. Implanting the at least one dopant at the oblique angle can change an electrostatic potential of a gate electrical contact of the transistor compared to implanting the at least one dopant at a non-oblique angle, and the change in the electrostatic potential of the gate electrical contact can shift the threshold voltage of the transistor.

Abstract translation: 用于调整半导体器件的阈值电压的方法包括以一定角度在半导体衬底中注入至少一种掺杂剂以形成晶体管的源极区和/或漏极区。 该角度与衬底的表面倾斜。 以角度植入至少一种掺杂剂会改变晶体管的平带电压并使晶体管的阈值电压发生偏移。 可以将至少一种掺杂剂或至少一种附加掺杂剂注入到晶体管的栅极电接触中。 以倾斜角度植入所述至少一种掺杂剂可以改变晶体管的栅极电接触的静电电位，以便以非倾斜角度注入至少一种掺杂剂，并且栅极电接触的静电电位的变化 可以移动晶体管的阈值电压。

公开(公告)号：US20150171158A1

公开(公告)日：2015-06-18

申请号：US14569975

申请日：2014-12-15

Applicant: Texas Instruments Incorporated

Inventor： Greg Charles BALDWIN ,  Kamel BENAISSA ,  Sarah LIU ,  Song Zhao

IPC: H01L49/02 ,  H01L21/265 ,  H01L21/8238

CPC classification number: H01L28/22 ,  G06F17/5072 ,  G06F17/5081 ,  H01L21/265 ,  H01L21/8238 ,  H01L27/0629 ,  H02J7/0044 ,  H02J7/025

Abstract: A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow.

Abstract translation: 一种将低TCR电阻添加到基准CMOS制造流程的方法。 在CMOS制造流程中形成低TCR电阻器的方法。 在CMOS制造流程中形成具有低TCR电阻器的n型和p型晶体管的方法。