公开(公告)号：US11848297B2

公开(公告)日：2023-12-19

申请号：US17364807

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Bo-Hsun Pan ,  Chien-Chang Li ,  Hung-Yu Chou ,  Shawn Martin O'Connor ,  Byron Lovell Williams ,  Jeffrey Alan West ,  Zi-Xian Zhan ,  Sheng-Wen Huang

IPC: H01L23/00 ,  H01L23/495 ,  H01L25/065

CPC classification number: H01L24/48 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/85 ,  H01L25/0655 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/48138 ,  H01L2224/48245 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48481 ,  H01L2224/85035 ,  H01L2224/85051 ,  H01L2924/182

Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.

公开(公告)号：US20230005874A1

公开(公告)日：2023-01-05

申请号：US17364807

申请日：2021-06-30

Applicant: Texas Instruments Incorporated

Inventor： Bo-Hsun Pan ,  Chien-Chang Li ,  Hung-Yu Chou ,  Shawn Martin O'Connor ,  Byron Lovell Williams ,  Jeffrey Alan West ,  Zi-Xian Zhan ,  Sheng-Wen Huang

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/495

Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.