公开(公告)号：US09564395B2

公开(公告)日：2017-02-07

申请号：US14809482

申请日：2015-07-27

申请人： MediaTek Inc.

发明人： Hsing-Chih Liu ,  Chia-Hao Yang ,  Ying-Chih Chen

IPC分类号： H01L23/48 ,  H01L23/522 ,  H01L23/538 ,  H01L23/528 ,  H01L23/50 ,  H01L23/495 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L25/0655 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/5221 ,  H01L23/528 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/0612 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48138 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48479 ,  H01L2224/4903 ,  H01L2224/4909 ,  H01L2224/4911 ,  H01L2224/4912 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/4945 ,  H01L2224/73265 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/4554

摘要： A semiconductor package structure includes a base. A first die is mounted on the base. The first die comprises a plurality of first pads with a first pad area arranged in a first tier. A plurality of second pads with a second pad area is arranged in a second tier. A second die is mounted on the base. The second die includes a plurality of third pads arranged in a third tier. A first bonding wire has two terminals respectively coupled to one of the first pads and one of the third pads. A second bonding wire has two terminals respectively coupled to one of the third pads and one of the second pads.

摘要翻译： 半导体封装结构包括基底。 第一个模具安装在基座上。 第一管芯包括多个第一焊盘，第一焊盘区域布置在第一层中。 具有第二焊盘区域的多个第二焊盘被布置在第二层中。 第二个模具安装在基座上。 第二管芯包括布置在第三层中的多个第三焊盘。 第一接合线具有分别耦合到第一焊盘之一和第三焊盘中的一个的两个端子。 第二接合线具有分别耦合到第三焊盘之一和第二焊盘之一的两个端子。

公开(公告)号：US09349707B1

公开(公告)日：2016-05-24

申请号：US14609896

申请日：2015-01-30

申请人： Invensas Corporation

发明人： Zhuowen Sun ,  Yong Chen ,  Kyong-Mo Bang

IPC分类号： H01L23/02 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC分类号： H01L25/0652 ,  H01L21/486 ,  H01L23/13 ,  H01L23/34 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/11 ,  H01L24/17 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L25/50 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/16057 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16165 ,  H01L2224/16235 ,  H01L2224/32145 ,  H01L2224/4502 ,  H01L2224/48138 ,  H01L2224/48148 ,  H01L2224/48165 ,  H01L2224/48235 ,  H01L2224/4824 ,  H01L2224/49174 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/1511 ,  H01L2924/152 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/3701 ,  H01L2224/45099

摘要： An apparatus relates generally to a microelectronic assembly. In this apparatus, a first substrate and a second substrate each have opposing surfaces. Contact arrangements are disposed on a surface of the first substrate, including: first contacts disposed as a ring to provide a first array of the contact arrangements on such surface; and second contacts disposed interior to the ring of the first contacts to provide a second array of the contact arrangements on the first surface. The first contacts and the second contacts are for interconnection with first microelectronic dies and second microelectronic dies. The second microelectronic dies are disposed below the first microelectronic dies in same a package as the first microelectronic dies. The first microelectronic dies and the second microelectronic dies include at least two ranks thereof for commonly sharing the first contacts and the second contacts among the first microelectronic dies and the second microelectronic dies.

摘要翻译： 装置一般涉及微电子组件。 在该装置中，第一基板和第二基板各自具有相对的表面。 接触装置设置在第一基板的表面上，包括：作为环设置的第一触点，以在该表面上提供接触装置的第一阵列; 以及第二触点，其设置在第一触头的环的内部，以在第一表面上提供接触装置的第二阵列。 第一触点和第二触点用于与第一微电子管芯和第二微电子管芯互连。 第二微电子管芯以与第一微电子管芯相同的封装设置在第一微电子管芯的下方。 第一微电子管芯和第二微电子管芯包括至少两个等级，用于共同共享第一微触点和第一微电子管芯与第二微电子管芯之间的第二触点。

公开(公告)号：US09099331B2

公开(公告)日：2015-08-04

申请号：US14585334

申请日：2014-12-30

申请人： ROHM CO., LTD.

发明人： Keiji Okumura

IPC分类号： H01L23/495 ,  H01L25/07 ,  H01L23/00

CPC分类号： H01L25/072 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/09 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/04 ,  H01L25/18 ,  H01L27/0629 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48138 ,  H01L2224/48139 ,  H01L2224/48157 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48471 ,  H01L2224/4903 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/85423 ,  H01L2224/85447 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/2065 ,  H01L2924/20651 ,  H01L2924/00015 ,  H01L2924/00012

摘要： Provided is a semiconductor device which includes a bonding wire, one end of which is connected to a bipolar device, the other end of which is connected to a conductive member, and the center of which is connected to a unipolar device, said semiconductor device being capable of improving the reliability of wire bonding. A package (4) includes a die pad (61), a source lead (63), a first MOSFET (11), and a first Schottky barrier diode (21). A source electrode (11S) of the first MOSFET (11), an anode electrode (21A) of the first Schottky barrier diode (21), and the source lead (63) are electrically connected by the bonding wire (31), one end of which is bonded to the source electrode (11S) of the first MOSFET (11), the other end of which is bonded to the source lead (63), and the center of which is bonded to the anode electrode (21A) of the first Schottky barrier diode (21).

公开(公告)号：US20240355717A1

公开(公告)日：2024-10-24

申请号：US18636035

申请日：2024-04-15

申请人： Navitas Semiconductor Limited

发明人： Alfred Hesener ,  Daniel M. Kinzer ,  Vincent Dessard ,  Marco Giandalia

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L25/065 ,  H03K17/687

CPC分类号： H01L23/49575 ,  H01L23/49562 ,  H01L24/08 ,  H01L24/48 ,  H01L25/0652 ,  H03K17/6871 ,  H01L2224/08145 ,  H01L2224/08245 ,  H01L2224/48138 ,  H01L2224/48175 ,  H01L2924/01029 ,  H01L2924/0493 ,  H01L2924/1205 ,  H01L2924/13091 ,  H01L2924/182 ,  H03K2217/0063 ,  H03K2217/0072

摘要： An electronic system is disclosed. The electronic system includes an electronic package having a base with a plurality of external terminals, and further having an electrically insulative material at least partially encapsulating the base, a controller circuit disposed within the electronic package and referenced to a first ground, a first and second driver circuits disposed within the electronic package and referenced to a second ground and arranged to receive isolated control signals from the controller circuit, and a bidirectional switch disposed within the electronic package and referenced to the second ground and arranged to receive drive signals from the first and second driver circuits. In one aspect, the first and second driver circuits are isolated from the controller circuit via capacitors, or magnetics, or optocouplers, or magneto resistors.

公开(公告)号：US11848297B2

公开(公告)日：2023-12-19

申请号：US17364807

申请日：2021-06-30

申请人： Texas Instruments Incorporated

发明人： Bo-Hsun Pan ,  Chien-Chang Li ,  Hung-Yu Chou ,  Shawn Martin O'Connor ,  Byron Lovell Williams ,  Jeffrey Alan West ,  Zi-Xian Zhan ,  Sheng-Wen Huang

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L25/065

CPC分类号： H01L24/48 ,  H01L23/4952 ,  H01L23/49575 ,  H01L24/45 ,  H01L24/85 ,  H01L25/0655 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/45644 ,  H01L2224/45664 ,  H01L2224/48138 ,  H01L2224/48245 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48481 ,  H01L2224/85035 ,  H01L2224/85051 ,  H01L2924/182

摘要： In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions spaced from the die mount portion; a semiconductor die over the die mount portion having bond pads on an active surface facing away from the package substrate; non-gold bond wires forming electrical connections between at least one of the bond pads and one of the lead portions of the package substrate; a bond stitch on bump connection formed between one of the non-gold bond wires and a bond pad of the semiconductor die, comprising a stitch bond formed on a flex stud bump; and dielectric material covering a portion of the package substrate, the semiconductor die, the non-gold bond wires, the stitch bond and the flex stud bump, forming a packaged semiconductor device.

公开(公告)号：US09837326B2

公开(公告)日：2017-12-05

申请号：US15245700

申请日：2016-08-24

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Akira Yajima

IPC分类号： H01L21/66 ,  H01L21/324 ,  H01L21/4763 ,  H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC分类号： H01L22/32 ,  G11C29/06 ,  G11C29/48 ,  G11C2029/5602 ,  H01L21/324 ,  H01L21/47635 ,  H01L22/14 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/03009 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05583 ,  H01L2224/05655 ,  H01L2224/05686 ,  H01L2224/06102 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48138 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/04941 ,  H01L2924/00014 ,  H01L2924/014

摘要： To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.

公开(公告)号：US20240363497A1

公开(公告)日：2024-10-31

申请号：US18641849

申请日：2024-04-22

申请人： Infineon Technologies AG

发明人： Andressa COLVERO SCHITTLER ,  Christian MÜLLER

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L25/065

CPC分类号： H01L23/49506 ,  H01L23/49575 ,  H01L24/08 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/08145 ,  H01L2224/08245 ,  H01L2224/48138 ,  H01L2224/48155 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/1306 ,  H01L2924/182

摘要： A semiconductor module arrangement includes a substrate including a dielectric insulation layer and a first metallization layer arranged on a surface of the dielectric insulation layer, wherein the first metallization layer comprises a first section, a second section, and a third section, and a first semiconductor body and an identical second semiconductor body arranged on the first metallization layer, wherein each of the first semiconductor body and the second semiconductor body has a first contact pad, a second contact pad, and a third contact pad arranged on a top side of the respective semiconductor body that faces away from the substrate, wherein the third contact pad of the first semiconductor body is electrically coupled to the third section of the first metallization layer by means of a first electrical connection element, the third contact pad of the second semiconductor body is electrically coupled to the third section of the first metallization layer by means of a second electrical connection element, the semiconductor module arrangement further includes at least one third terminal element arranged on the third section, a first current path between the third contact pad of the first semiconductor body and the at least one third terminal element provides identical voltage and current transfer characteristics as a second current path between the third contact pad of the second semiconductor body and the at least one third terminal element, and each of the first and second electrical connection elements includes one or more bonding wires, one or more bonding ribbons, a connection rail, or a section of an additional metallization layer of the substrate that is contacted by corresponding vias.

公开(公告)号：US20180068910A1

公开(公告)日：2018-03-08

申请号：US15798369

申请日：2017-10-30

申请人： RENESAS ELECTRONICS CORPORATION

发明人： Akira YAJIMA

IPC分类号： H01L21/66 ,  G11C29/48 ,  H01L25/065 ,  H01L21/324 ,  H01L21/4763 ,  G11C29/06 ,  H01L23/00 ,  H01L23/31 ,  G11C29/56

CPC分类号： H01L22/32 ,  G11C29/06 ,  G11C29/48 ,  G11C2029/5602 ,  H01L21/324 ,  H01L21/47635 ,  H01L22/14 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0655 ,  H01L25/0657 ,  H01L2224/02311 ,  H01L2224/02331 ,  H01L2224/02377 ,  H01L2224/03009 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05583 ,  H01L2224/05655 ,  H01L2224/05686 ,  H01L2224/06102 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48138 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/04941 ,  H01L2924/00014 ,  H01L2924/014

摘要： To enhance reliability of a test by suppressing defective bonding of a solder in the test of a semiconductor device, a method of manufacturing the semiconductor device includes: preparing a semiconductor wafer that includes a first pad electrode provided with a first cap film and a second pad electrode provided with a second cap film. Further, a polyimide layer that includes a first opening on the first pad electrode and a second opening on the second pad electrode is formed, and then, a rearrangement wiring that is connected to the second pad electrode via the second opening is formed. Next, an opening is formed in the polyimide layer such that an organic reaction layer remains on each of the first pad electrode and a bump land of the rearrangement wiring, then heat processing is performed on the semiconductor wafer, and then, a bump is formed on the rearrangement wiring.

公开(公告)号：US09129962B1

公开(公告)日：2015-09-08

申请号：US14271792

申请日：2014-05-07

申请人： MediaTek Inc.

发明人： Hsing-Chih Liu ,  Chia-Hao Yang ,  Ying-Chih Chen

IPC分类号： H01L23/48 ,  H01L23/522 ,  H01L23/538 ,  H01L23/528 ,  H01L23/50 ,  H01L23/495

CPC分类号： H01L25/0655 ,  H01L23/49575 ,  H01L23/50 ,  H01L23/5221 ,  H01L23/528 ,  H01L23/5381 ,  H01L23/5386 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/0612 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48137 ,  H01L2224/48138 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48479 ,  H01L2224/4903 ,  H01L2224/4909 ,  H01L2224/4911 ,  H01L2224/4912 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/4945 ,  H01L2224/73265 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2924/00015 ,  H01L2924/00 ,  H01L2224/4554

摘要： The invention provides a semiconductor package structure. The semiconductor package structure includes a base. A first die is mounted on the base. The first die comprises a plurality of first pads with a first pad area arranged in a first tier. A plurality of second pads with a second pad area is arranged in a second tier. A second die is mounted on the base. The second die comprises a plurality of third pads with the first pad area and a plurality of fourth pads with the second pad area alternately arranged in a third tier. A first bonding wire has two terminals respectively coupled to one of the first pads and one of the fourth pads. A second bonding wire has two terminals respectively coupled to one of the third pads and one of the second pads.

摘要翻译： 本发明提供一种半导体封装结构。 半导体封装结构包括基底。 第一个模具安装在基座上。 第一管芯包括多个第一焊盘，第一焊盘区域布置在第一层中。 具有第二焊盘区域的多个第二焊盘被布置在第二层中。 第二个模具安装在基座上。 第二管芯包括具有第一焊盘区域的多个第三焊盘和具有第二焊盘区域的多个第四焊盘，其交替地布置在第三层中。 第一接合线具有分别耦合到第一焊盘之一和第四焊盘之一的两个端子。 第二接合线具有分别耦合到第三焊盘之一和第二焊盘之一的两个端子。

公开(公告)号：US08970020B2

公开(公告)日：2015-03-03

申请号：US14348602

申请日：2012-06-18

申请人： Keiji Okumura

发明人： Keiji Okumura

IPC分类号： H01L23/495 ,  H01L27/06 ,  H01L25/04 ,  H01L25/18 ,  H01L23/00

CPC分类号： H01L25/072 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/09 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/04 ,  H01L25/18 ,  H01L27/0629 ,  H01L2224/04042 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/291 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48011 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48138 ,  H01L2224/48139 ,  H01L2224/48157 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48471 ,  H01L2224/4903 ,  H01L2224/49109 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/73265 ,  H01L2224/78313 ,  H01L2224/85423 ,  H01L2224/85447 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/2065 ,  H01L2924/20651 ,  H01L2924/00015 ,  H01L2924/00012

摘要： Provided is a semiconductor device which includes a bonding wire, one end of which is connected to a bipolar device, the other end of which is connected to a conductive member, and the center of which is connected to a unipolar device, said semiconductor device being capable of improving the reliability of wire bonding. A package (4) includes a die pad (61), a source lead (63), a first MOSFET (11), and a first Schottky barrier diode (21). A source electrode (11S) of the first MOSFET (11), an anode electrode (21A) of the first Schottky barrier diode (21), and the source lead (63) are electrically connected by the bonding wire (31), one end of which is bonded to the source electrode (11S) of the first MOSFET (11), the other end of which is bonded to the source lead (63), and the center of which is bonded to the anode electrode (21A) of the first Schottky barrier diode (21).

摘要翻译： 提供一种半导体器件，其包括接合线，其一端连接到双极器件，其另一端连接到导电构件，并且其中心连接到单极器件，所述半导体器件为 能够提高引线接合的可靠性。 封装（4）包括管芯焊盘（61），源极引线（63），第一MOSFET（11）和第一肖特基势垒二极管（21）。 第一MOSFET（11）的源电极（11S），第一肖特基势垒二极管（21）的阳极电极（21A）和源极引线（63）通过接合线（31）电连接，一端 其结合到第一MOSFET（11）的源电极（11S），其另一端与源极（63）接合，并且其中心与第一MOSFET（11）的阳极电极（21A）接合， 第一肖特基势垒二极管（21）。