公开(公告)号：US08753944B2

公开(公告)日：2014-06-17

申请号：US13766847

申请日：2013-02-14

Applicant: Texas Instruments Incorporated

Inventor： Mahalingam Nandakumar ,  Brian Hornung ,  Terry James Bordelon, Jr. ,  Amitava Chatterjee

IPC: H01L21/336

CPC classification number: H01L29/66492 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833

Abstract: A method of fabricating a Metal-Oxide Semiconductor (MOS) transistor includes providing a substrate having a substrate surface doped with a second dopant type and a gate stack over the substrate surface, and a masking pattern on the substrate surface which exposes a portion of the substrate surface for ion implantation. A first pocket implantation uses the second dopant type with the masking pattern on the substrate surface. At least one retrograde gate edge diode leakage (GDL) reduction pocket implantation uses the first dopant type with the masking pattern on the substrate surface. The first pocket implant and retrograde GDL reduction pocket implant are annealed. After annealing, the first pocket implant provides first pocket regions and the retrograde GDL reduction pocket implant provides an overlap with the first pocket regions to form a first counterdoped pocket portion within the first pocket regions.

Abstract translation: 制造金属氧化物半导体（MOS）晶体管的方法包括提供具有掺杂有第二掺杂剂类型的衬底表面的衬底和在衬底表面上的栅极堆叠，以及在衬底表面上的掩模图案，其暴露部分 用于离子注入的衬底表面。 第一种口袋植入使用具有衬底表面上的掩模图案的第二掺杂剂类型。 至少一个逆向栅极边缘二极管漏极（GDL）还原袋注入在衬底表面上使用具有掩模图案的第一掺杂剂类型。 第一口袋植入物和逆行GDL还原袋植入物进行退火。 在退火之后，第一口袋植入件提供第一袋区域，并且逆行GDL减少袋植入物提供与第一袋区域的重叠，以在第一袋区域内形成第一反向袋部分。

公开(公告)号：US09722021B2

公开(公告)日：2017-08-01

申请号：US14843082

申请日：2015-09-02

Applicant: Texas Instruments Incorporated

Inventor： Bruce Lynn Pickelsimer ,  Patrick Robert Smith ,  Terry James Bordelon, Jr.

IPC: H01L21/225 ,  H01L29/06 ,  H01L29/788 ,  H01L29/66 ,  H01L21/306 ,  H01L21/283

CPC classification number: H01L29/0649 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/283 ,  H01L21/30604 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/788

Abstract: An integrated circuit and method has an isolated well with an improved isolated well contact. The well contact diffusion is isolated from a device diffusion of opposite conductivity type within the isolated well by an isolation transistor gate.

公开(公告)号：US10593752B2

公开(公告)日：2020-03-17

申请号：US15636173

申请日：2017-06-28

Applicant: Texas Instruments Incorporated

Inventor： Bruce Lynn Pickelsimer ,  Patrick Robert Smith ,  Terry James Bordelon, Jr.

IPC: H01L29/06 ,  H01L29/788 ,  H01L29/66 ,  H01L21/225 ,  H01L21/306 ,  H01L21/283 ,  H01L29/78 ,  H01L21/265

Abstract: An integrated circuit and method has an isolated well with an improved isolated well contact. The well contact diffusion is isolated from a device diffusion of opposite conductivity type within the isolated well by an isolation transistor gate.