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公开(公告)号：US20170149512A1
公开(公告)日：2017-05-25
申请号：US14946360
申请日：2015-11-19
摘要： An RF or other high frequency transceiver including a loopback reference channel for measurement of an absolute power level. A transmit channel in the transceiver includes a programmable power amplifier that can be controlled to operate at a selected power level, and a receive channel including a receive amplifier, mixers, filters, and analog-to-digital converters. The loopback reference channel includes a self-biased amplifier, followed by a series of buffers that generate a square wave from the received signal, and an attenuator applying an attenuation gain to the square wave. The transmit power at a programmed power level can be calculated from ratios of a measured power level of a transmitted signal as received by the receive channel to the measured power level of the transmitted signal using the loopback reference channel.
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2.发明授权SoC transceiver with single ended/differential modes, tunable capacitor and latch 有权具有单端/差分模式的SoC收发器，可调谐电容器和锁存器公开(公告)号：US09331734B2
公开(公告)日：2016-05-03
申请号：US14740961
申请日：2015-06-16
CPC分类号： H04B1/401 , H03F3/24 , H04B1/0458 , H04B1/18 , H04B2001/0408
摘要： A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to operate in a single ended mode and in a differential mode. Two interface pins are provided for coupling the transceiver to an antenna via a matching network, wherein the two interface pins are shareably coupled to the transmitter and to the receiver. A tunable capacitor is coupled to differential signal lines of the configurable portion, wherein the tunable capacitor is configured to be tuned to optimize impedance matching of the configurable portion for each mode of operation.
摘要翻译： 芯片上的系统（SoC）包括收发器，其包括发射器和接收器，其中发射器和接收器中的至少一个具有可配置部分，其可被配置为以单端模式和差分模式操作。 提供两个接口引脚用于通过匹配网络将收发器耦合到天线，其中两个接口引脚可共享地耦合到发射器和接收器。 可调电容器耦合到可配置部分的差分信号线，其中可调谐电容器被配置为调整以优化每个操作模式的可配置部分的阻抗匹配。
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公开(公告)号：US09176188B2
公开(公告)日：2015-11-03
申请号：US14137994
申请日：2013-12-20
发明人： Sudipto Chakraborty , Jens Graul
IPC分类号： H04B3/46 , G01R31/317 , H04B17/00
CPC分类号： G01R31/31716 , G01R31/2822 , G01R31/3187 , H04B17/13 , H04B17/19
摘要： A system on a chip (SoC) includes a transceiver comprising a transmitter having a power amplifier and a receiver having a signal buffer. At least one of the transmitter and receiver has a configurable portion that can be configured to produce a range of waveforms (both in waveshape as well as duty cycle). A low cost built in self test (BIST) logic is coupled to the transceiver. The BIST logic is operable to calibrate the configurable portion of the transceiver to produce a waveform that has a selected harmonic component that has an amplitude that is less than a threshold value. Current consumed by the transceiver may be dynamically reduced by selecting an optimized waveform that has low harmonic components.
摘要翻译： 芯片上的系统（SoC）包括收发器，包括具有功率放大器的发射机和具有信号缓冲器的接收机。 发射器和接收器中的至少一个具有可配置部分，其可被配置为产生波形范围（波形以及占空比）。 内置自检（BIST）逻辑的低成本耦合到收发器。 BIST逻辑可操作地校准收发器的可配置部分以产生具有小于阈值的幅度的选定谐波分量的波形。 可以通过选择具有低谐波分量的优化波形来动态地减少收发器消耗的电流。
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公开(公告)号：US09692428B2
公开(公告)日：2017-06-27
申请号：US14137366
申请日：2013-12-20
发明人： Sudipto Chakraborty , Jens Graul
IPC分类号： H03L7/08 , H03L7/18 , H03L7/099 , H03L7/089 , H03L7/23 , H03L7/10 , H04B1/403 , H04B1/408 , H04B1/50
CPC分类号： H03L7/0802 , H03L7/0891 , H03L7/099 , H03L7/104 , H03L7/18 , H03L7/235 , H04B1/403 , H04B1/408 , H04B1/50
摘要： A self-calibrating shared-component dual synthesizer includes, for example, two frequency synthesizers that are adapted to operate (respectively) in transmit (TX) and receive (RX) modes. Each synthesizer can be selectively arranged to vary and optimize the phase noise in accordance with the TX and RX requirements associated with each mode as well as independently optimized for flexible low area floorplan to achieve low power, spectral fidelity and reduced test time, low cost built in self-calibration. The two frequency synthesizers are also adapted to provide a built-in self-test signals used for intermodulation testing and calibration.
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公开(公告)号：US20170141803A1
公开(公告)日：2017-05-18
申请号：US15350094
申请日：2016-11-13
CPC分类号： H04B1/06 , H04L27/06 , H04W52/0229 , H04W52/0254 , Y02D70/166
摘要： A wireless wake-up receiver includes multiple signal chains each signal chain being coupled to continuously receive a signal from a respective antenna and to provide a respective detected pattern at a signal chain output. Each signal chain includes a first path having a mixer-first architecture and operates in a bandpass-mode using differential signals. The wireless wake-up receiver also includes a digital correlator operable to receive the respective detected patterns and to determine whether one of the respective detected patterns is equal to a desired pattern.
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公开(公告)号：US20150180594A1
公开(公告)日：2015-06-25
申请号：US14137366
申请日：2013-12-20
发明人： Sudipto Chakraborty , Jens Graul
CPC分类号： H03L7/0802 , H03L7/0891 , H03L7/099 , H03L7/104 , H03L7/18 , H03L7/235 , H04B1/403 , H04B1/408 , H04B1/50
摘要： A self-calibrating shared-component dual synthesizer includes, for example, two frequency synthesizers that are adapted to operate (respectively) in transmit (TX) and receive (RX) modes. Each synthesizer can be selectively arranged to vary and optimize the phase noise in accordance with the TX and RX requirements associated with each mode as well as independently optimized for flexible low area floorplan to achieve low power, spectral fidelity and reduced test time, low cost built in self-calibration. The two frequency synthesizers are also adapted to provide a built-in self-test signals used for intermodulation testing and calibration.
摘要翻译： 自校准共享部件双合成器包括例如适于在发射（TX）和接收（RX）模式中分别操作的两个频率合成器。 每个合成器可以选择性地布置成根据与每个模式相关联的TX和RX要求来改变和优化相位噪声，并且针对灵活的低面积平面图进行独立优化，以实现低功率，频谱保真度和缩短的测试时间，低成本内置 进行自校准。 两个频率合成器也适用于提供用于互调测试和校准的内置自测信号。
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公开(公告)号：US20150015222A1
公开(公告)日：2015-01-15
申请号：US13938085
申请日：2013-07-09
IPC分类号： G05F1/46
CPC分类号： G05F1/56
摘要： Voltage regulators are disclosed herein. An embodiment of a voltage regulator includes a MOS-type pass transistor, wherein a first node of the pass transistor is connectable to a voltage source and wherein a second node of the pass transistor is connected to the output of the voltage regulator. The voltage regulator also includes an error amplifier having a reference input and an output, the output being connected to the gate of the pass transistor, and the reference input being connected to a reference voltage source.
摘要翻译： 本文公开了电压调节器。 电压调节器的实施例包括MOS型通过晶体管，其中传输晶体管的第一节点可连接到电压源，并且其中传输晶体管的第二节点连接到电压调节器的输出端。 电压调节器还包括具有参考输入和输出的误差放大器，输出端连接到传输晶体管的栅极，参考输入端连接到参考电压源。
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公开(公告)号：US09813169B2
公开(公告)日：2017-11-07
申请号：US14946360
申请日：2015-11-19
摘要： An RF or other high frequency transceiver including a loopback reference channel for measurement of an absolute power level. A transmit channel in the transceiver includes a programmable power amplifier that can be controlled to operate at a selected power level, and a receive channel including a receive amplifier, mixers, filters, and analog-to-digital converters. The loopback reference channel includes a self-biased amplifier, followed by a series of buffers that generate a square wave from the received signal, and an attenuator applying an attenuation gain to the square wave. The transmit power at a programmed power level can be calculated from ratios of a measured power level of a transmitted signal as received by the receive channel to the measured power level of the transmitted signal using the loopback reference channel.
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公开(公告)号：US20150280772A1
公开(公告)日：2015-10-01
申请号：US14740961
申请日：2015-06-16
CPC分类号： H04B1/401 , H03F3/24 , H04B1/0458 , H04B1/18 , H04B2001/0408
摘要： A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to operate in a single ended mode and in a differential mode. Two interface pins are provided for coupling the transceiver to an antenna via a matching network, wherein the two interface pins are shareably coupled to the transmitter and to the receiver. A tunable capacitor is coupled to differential signal lines of the configurable portion, wherein the tunable capacitor is configured to be tuned to optimize impedance matching of the configurable portion for each mode of operation.
摘要翻译： 芯片上的系统（SoC）包括收发器，其包括发射器和接收器，其中发射器和接收器中的至少一个具有可配置部分，其可被配置为以单端模式和差分模式操作。 提供两个接口引脚用于通过匹配网络将收发器耦合到天线，其中两个接口引脚可共享地耦合到发射器和接收器。 可调电容器耦合到可配置部分的差分信号线，其中可调谐电容器被配置为调整以优化每个操作模式的可配置部分的阻抗匹配。
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公开(公告)号：US09088334B2
公开(公告)日：2015-07-21
申请号：US13748008
申请日：2013-01-23
CPC分类号： H04B1/401 , H03F3/24 , H04B1/0458 , H04B1/18 , H04B2001/0408
摘要： A system on a chip (SoC) includes a transceiver comprising a transmitter and a receiver, wherein at least one of the transmitter and receiver has a configurable portion that can be configured to operate in a single ended mode and in a differential mode. Two interface pins are provided for coupling the transceiver to an antenna via a matching network, wherein the two interface pins are shareably coupled to the transmitter and to the receiver. A tunable capacitor is coupled to differential signal lines of the configurable portion, wherein the tunable capacitor is configured to be tuned to optimize impedance matching of the configurable portion for each mode of operation.
摘要翻译： 芯片上的系统（SoC）包括收发器，其包括发射器和接收器，其中发射器和接收器中的至少一个具有可配置部分，其可被配置为以单端模式和差分模式操作。 提供两个接口引脚用于通过匹配网络将收发器耦合到天线，其中两个接口引脚可共享地耦合到发射器和接收器。 可调电容器耦合到可配置部分的差分信号线，其中可调谐电容器被配置为调整以优化每个操作模式的可配置部分的阻抗匹配。
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