公开(公告)号：US5933618A

公开(公告)日：1999-08-03

申请号：US550218

申请日：1995-10-30

申请人： Thang M. Tran ,  James K. Pickett ,  Rupaka Mahalingaiah

发明人： Thang M. Tran ,  James K. Pickett ,  Rupaka Mahalingaiah

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3812 ,  G06F12/0804 ,  G06F12/0846 ,  G06F12/0864 ,  G06F9/30054 ,  G06F9/30152 ,  G06F9/3806 ,  G06F9/3814 ,  G06F9/3832 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3848 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863

摘要： A microprocessor including a reorder buffer configured to store speculative register values regarding a particular register is provided. One value is stored for each set of concurrently decoded instructions which are outstanding within the microprocessor, reflecting the updates of each instruction within the set which updates the register. Additionally, the reorder buffer stores a set of constants indicative of the modification of the register by each instruction within the set of concurrently decoded instructions. Recovery from a mispredicted branch instruction (or from an instruction which causes an exception, a TRAP instruction, or an interrupt) may be achieved by utilizing the constants to adjust the result generated for the set of concurrently decoded instructions including the mispredicted branch instruction. The constants generated to indicate the modifications of the particular register may additionally allow multiple instructions having a dependency for the particular register to execute in parallel.

摘要翻译： 提供了一种微处理器，其包括配置为存储关于特定寄存器的推测寄存器值的重排序缓冲器。 对于在微处理器内未完成的每组并行解码的指令存储一个值，反映了更新寄存器的集合内的每个指令的更新。 此外，重排序缓冲器存储指示该并发解码指令集内的每个指令对寄存器进行修改的一组常数。 可以通过利用常数来调整针对包括错误预测的分支指令的并行解码指令集合生成的结果来实现从错误预测的分支指令（或来自导致异常，TRAP指令或中断的指令）的恢复。 为了指示特定寄存器的修改产生的常数可另外允许具有对特定寄存器的依赖性的多个指令并行执行。

公开(公告)号：US5892936A

公开(公告)日：1999-04-06

申请号：US879520

申请日：1997-06-20

申请人： Thang M. Tran ,  James K. Pickett ,  Rupaka Mahalingaiah

发明人： Thang M. Tran ,  James K. Pickett ,  Rupaka Mahalingaiah

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3812 ,  G06F9/30101 ,  G06F9/30152 ,  G06F9/3016 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3824 ,  G06F9/3828 ,  G06F9/3832 ,  G06F9/3842

摘要： A superscalar microprocessor configured to speculatively generate register values associated with a particular register is provided. Multiple register values are generated in parallel, wherein each speculatively generated register value accounts for modifications of the register value by each of the instructions prior to the instruction for which the register value is generated. Instructions which are dependent upon each other for the register values thus generated may be executed concurrently. In one specific embodiment, the present microprocessor generates register values for the ESP register. The speculatively generated register value resulting from the modifications performed by the instructions decoded during a clock cycle is stored in a speculative register file along with constants used to generate the register value associated with each individual instruction. When a mispredicted branch instruction is detected, the register value generated during the decode of the mispredicted branch instruction may be adjusted using the stored constants. The adjustment performed reflects the value of the register at the execution of the mispredicted branch instruction.

摘要翻译： 提供了配置成推测性地生成与特定寄存器相关联的寄存器值的超标量微处理器。 并行产生多个寄存器值，其中每个推测产生的寄存器值在生成寄存器值的指令之前考虑每个指令对寄存器值的修改。 对于由此生成的寄存器值彼此依赖的指令可以同时执行。 在一个具体实施例中，本微处理器产生ESP寄存器的寄存器值。 由在时钟周期期间解码的指令执行的修改产生的推测产生的寄存器值与用于生成与每个单独指令相关联的寄存器值的常数一起存储在推测寄存器文件中。 当检测到错误预测的分支指令时，可以使用存储的常数来调整在误预测分支指令的解码期间生成的寄存器值。 执行的调整反映了在执行错误预测的分支指令时寄存器的值。

公开(公告)号：US6085302A

公开(公告)日：2000-07-04

申请号：US633351

申请日：1996-04-17

申请人： Rupaka Mahalingaiah ,  Thang M. Tran

发明人： Rupaka Mahalingaiah ,  Thang M. Tran

IPC分类号： G06F9/355 ,  G06F9/38 ,  G06F12/02

CPC分类号： G06F9/355 ,  G06F9/3885

摘要： A microprocessor including address generation units configured to perform address generation for memory operations is provided. A reservation station associated with one of the address generation units receives the displacement from an instruction and an indication of the selected segment register upon decode of the instruction in a corresponding decode unit within the microprocessor. The displacement and segment base address from the selected segment register are added in the reservation station while the register operands for the instruction are requested. If the register operands are provided upon request (as opposed to a reorder buffer tag), the displacement/base sum and register operands are passed to the address generation unit. The address generation unit adds the displacement/base sum to the register operands, thereby forming the linear address. If register operands are not provided upon request (i.e. one or more reorder buffer tags are received instead of the corresponding register operand), then the reservation station stores the displacement/base sum and register operands/tags. Once each register operand has been provided, the displacement/base sum and register operands are conveyed to the address generation unit. Data address generation responsibilities are thereby fulfilled by the address generation units. Since the functional units of the microprocessor are relieved of address generation responsibilities, the functional units may be simplified.

摘要翻译： 提供一种微处理器，包括被配置为执行存储器操作的地址生成的地址生成单元。 与地址生成单元中的一个相关联的预约站在微处理器中的对应解码单元中的指令解码后，从指令接收所选择的段寄存器的指示和指示。 来自所选段寄存器的位移和段基地址被添加到保留站中，同时请求指令的寄存器操作数。 如果根据请求提供寄存器操作数（与重新排序缓冲器标签相反），则将位移/基和和寄存器操作数传递给地址生成单元。 地址生成单元将位移/基数和加到寄存器操作数，从而形成线性地址。 如果根据请求不提供寄存器操作数（即接收一个或多个重新排序缓冲器标签而不是相应的寄存器操作数），则保留站存储位移/基本和和寄存器操作数/标签。 一旦提供了每个寄存器操作数，则位移/基和和寄存器操作数被传送到地址生成单元。 地址生成单元由此实现数据地址生成责任。 由于微处理器的功能单元减轻了地址生成责任，因此功能单元可以被简化。

公开(公告)号：US6065103A

公开(公告)日：2000-05-16

申请号：US991915

申请日：1997-12-16

申请人： Thang M. Tran ,  Rupaka Mahalingaiah

发明人： Thang M. Tran ,  Rupaka Mahalingaiah

IPC分类号： G06F9/38 ,  G06F12/00

CPC分类号： G06F9/3842 ,  G06F9/3834

摘要： A speculative store buffer is speculatively updated in response to speculative store memory operations buffered by a load/store unit in a microprocessor. Instead of performing dependency checking for load memory operations among the store memory operations buffered by the load/store unit, the load/store unit may perform a lookup in the speculative store buffer. If a hit is detected in the speculative store buffer, the speculative state of the memory location is forwarded from the speculative store buffer. The speculative state corresponds to the most recent speculative store memory operation, even if multiple speculative store memory operations are buffered by the load/store unit. Since dependency checking against the memory operation buffers is not performed, the dependency checking limitations as to the size of these buffers may be eliminated. The speed at which dependency checking can be performed may in large part be determined by the number of storage locations within the speculative store buffer (as opposed to the number of memory operations which may be buffered in the memory operation buffers or buffers).

摘要翻译： 响应于由微处理器中的加载/存储单元缓冲的推测存储器操作，推测性地更新推测性存储缓冲器。 加载/存储单元可以在推测存储缓冲器中执行查找，而不是对由加载/存储单元缓冲的存储器存储器操作之间对加载存储器操作执行依赖性检查。 如果在推测存储缓冲区中检测到命中，则存储器位置的推测状态从推测性存储缓冲区转发。 即使多个推测存储器存储器操作被加载/存储单元缓冲，推测状态对应于最近的推测存储器存储器操作。 由于不执行对存储器操作缓冲器的依赖性检查，因此可以消除关于这些缓冲器的大小的依赖性检查限制。 可以执行依赖性检查的速度在很大程度上可以由推测性存储缓冲器内的存储位置的数量（与可能在存储器操作缓冲器或缓冲器中缓冲的存储器操作的数量相反）来确定。

公开(公告)号：US06269436B1

公开(公告)日：2001-07-31

申请号：US09392300

申请日：1999-09-08

申请人： Thang M. Tran ,  Rupaka Mahalingaiah

发明人： Thang M. Tran ,  Rupaka Mahalingaiah

IPC分类号： G06F1500

CPC分类号： G06F9/3806 ,  G01R31/318533 ,  G06F9/30054 ,  G06F9/30152 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3832 ,  G06F9/3844 ,  G06F9/3848 ,  G06F11/2236

摘要： A microprocessor is provided which is configured to predict return addresses for return instructions according to a return stack storage included therein. The return stack storage is a stack structure configured to store return addresses associated with previously detected call instructions. Return addresses may be predicted for return instructions early in the instruction processing pipeline of the microprocessor. In one embodiment, the return stack storage additionally stores a call tag and a return tag with each return address. The call tag and return tag respectively identify call and return instructions associated with the return address. These tags may be compared to a branch tag conveyed to the return prediction unit upon detection of a branch misprediction. The results of the comparisons may be used to adjust the contents of the return stack storage with respect to the misprediction. The microprocessor may continue to predict return addresses correctly following a mispredicted branch instruction.

摘要翻译： 提供微处理器，其被配置为根据其中包括的返回堆栈存储来预测返回指令的返回地址。 返回栈存储器是被配置为存储与先前检测到的调用指令相关联的返回地址的堆栈结构。 可以在微处理器的指令处理流水线的早期为返回指令预测返回地址。 在一个实施例中，返回堆栈存储器另外存储具有每个返回地址的呼叫标签和返回标签。 呼叫标签和返回标签分别标识与返回地址相关联的呼叫和返回指令。 这些标签可以与检测到分支错误预测时传送到返回预测单元的分支标签进行比较。 可以使用比较结果来调整返回堆栈存储器相对于错误预测的内容。 微处理器可以在错误预测的分支指令之后继续正确地预测返回地址。

公开(公告)号：US6014734A

公开(公告)日：2000-01-11

申请号：US153770

申请日：1998-09-15

申请人： Thang M. Tran ,  Rupaka Mahalingaiah

发明人： Thang M. Tran ,  Rupaka Mahalingaiah

IPC分类号： G01R31/3185 ,  G06F9/30 ,  G06F9/38 ,  G06F11/267

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/30152 ,  G06F9/3816 ,  G06F9/382 ,  G06F9/3832 ,  G06F9/3844 ,  G06F9/3848 ,  G01R31/318533 ,  G06F11/2236

摘要： A microprocessor is provided which is configured to predict return addresses for return instructions according to a return stack storage included therein. The return stack storage is a stack structure configured to store return addresses associated with previously detected call instructions. Return addresses may be predicted for return instructions early in the instruction processing pipeline of the microprocessor. In one embodiment, the return stack storage additionally stores a call tag and a return tag with each return address. The call tag and return tag respectively identify call and return instructions associated with the return address. These tags may be compared to a branch tag conveyed to the return prediction unit upon detection of a branch misprediction. The results of the comparisons may be used to adjust the contents of the return stack storage with respect to the misprediction. The microprocessor may continue to predict return addresses correctly following a mispredicted branch instruction.

摘要翻译： 提供微处理器，其被配置为根据其中包括的返回堆栈存储来预测返回指令的返回地址。 返回栈存储器是被配置为存储与先前检测到的调用指令相关联的返回地址的堆栈结构。 可以在微处理器的指令处理流水线的早期为返回指令预测返回地址。 在一个实施例中，返回堆栈存储器另外存储具有每个返回地址的呼叫标签和返回标签。 呼叫标签和返回标签分别标识与返回地址相关联的呼叫和返回指令。 这些标签可以与检测到分支错误预测时传送到返回预测单元的分支标签进行比较。 可以使用比较结果来调整返回堆栈存储器相对于错误预测的内容。 微处理器可以在错误预测的分支指令之后继续正确地预测返回地址。

公开(公告)号：US6016545A

公开(公告)日：2000-01-18

申请号：US991694

申请日：1997-12-16

申请人： Rupaka Mahalingaiah ,  Andrew McBride ,  Thang M. Tran

发明人： Rupaka Mahalingaiah ,  Andrew McBride ,  Thang M. Tran

IPC分类号： G06F9/38

CPC分类号： G06F9/3802 ,  G06F9/3844

摘要： A microprocessor stores cache-line-related data (e.g. branch predictions or predecode data, in the illustrated embodiments) in a storage which includes fewer storage locations than the number of cache lines in the instruction cache. Each storage location in the storage is mappable to multiple cache lines, any one of which can be associated with the data stored in the storage location. The storage may thereby be smaller than a storage which provides an equal number of storage locations as the number of cache lines in the instruction cache. Access time to the storage may be reduced, therefore providing for a higher frequency implementation. Still further, semiconductor substrate area occupied by the storage may be decreased. In one embodiment, the storage is indexed by a subset of the index bits used to index the instruction cache. The subset comprises the least significant bits of the cache index. In other words, the cache lines which share a particular storage location within the storage differ in the most significant cache index bits. Therefore, code which exhibits spatial locality may experience little conflict for the storage locations.

摘要翻译： 微处理器将包含比指令高速缓存中的高速缓存行的数量更少的存储位置的存储器中的高速缓存线相关数据（例如在所示实施例中的分支预测或预解码数据）存储在存储器中。 存储器中的每个存储位置可映射到多个高速缓存行，其中任何一个可以与存储在存储位置中的数据相关联。 因此，存储器可以小于提供与指令高速缓存中的高速缓存行数相同数量的存储位置的存储器。 可能减少对存储器的访问时间，因此提供更高频率的实现。 此外，可以减少由存储器占据的半导体衬底区域。 在一个实施例中，存储器被用于索引指令高速缓存的索引位的子集索引。 该子集包括高速缓存索引的最低有效位。 换句话说，在存储器中共享特定存储位置的高速缓存行在最重要的高速缓存索引位中不同。 因此，展示空间局部性的代码可能对存储位置的冲突很小。

公开(公告)号：US5787266A

公开(公告)日：1998-07-28

申请号：US603805

申请日：1996-02-20

申请人： William M. Johnson ,  Thang M. Tran ,  Rupaka Mahalingaiah

发明人： William M. Johnson ,  Thang M. Tran ,  Rupaka Mahalingaiah

IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F9/00

CPC分类号： G06F9/30167 ,  G06F9/30101 ,  G06F9/30152 ,  G06F9/30163 ,  G06F9/382 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A microprocessor employing an apparatus for performing special register writes without serialization is provided. The apparatus detects special register write instructions when the instructions are dispatched, and stores an indication of the write in a special register dependency block. Instructions subsequent to the special register write instruction are examined for both explicit and implicit dependencies upon the special register write. If a dependency is detected with respect to a particular instruction, the instruction is dispatched to a reservation station along with an indication of the dependency. Instructions subsequent to the special register write instruction which are not dependent upon the special register are dispatched without an indication of special register dependency. Instructions without dependencies may speculatively execute prior to instructions with dependencies, or even prior to the special register write instruction. In one particular embodiment employing the x86 microprocessor architecture, the microprocessor detects updates to the DS, ES, FS, and GS segment registers (i.e. the data segment registers). Updates to other segment registers are serialized.

摘要翻译： 提供了一种使用不进行串行化来执行特殊寄存器写入的装置的微处理器。 当调度指令时，该设备检测特殊寄存器写指令，并将写入的指示存储在特殊寄存器依赖块中。 在特殊寄存器写入指令之后的指令将针对特殊寄存器写入时的显式和隐式依赖性进行检查。 如果相对于特定指令检测到依赖关系，则将该指令与依赖性的指示一起发送到保留站。 在不依赖于特殊寄存器的特殊寄存器写入指令之后的指令被调度，而不指示特殊寄存器依赖性。 没有依赖性的指令可以在具有依赖性的指令之前，甚至在特殊寄存器写指令之前推测执行。 在采用x86微处理器架构的一个特定实施例中，微处理器检测对DS，ES，FS和GS段寄存器（即，数据段寄存器）的更新。 其他段寄存器的更新被序列化。

公开(公告)号：US5835968A

公开(公告)日：1998-11-10

申请号：US633302

申请日：1996-04-17

申请人： Rupaka Mahalingaiah ,  Thang M. Tran

发明人： Rupaka Mahalingaiah ,  Thang M. Tran

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F12/10

CPC分类号： G06F12/0875 ,  G06F9/3826 ,  G06F9/3832

摘要： An apparatus including address generation units, corresponding reservation stations, and a speculative register file is provided. Decode units provide memory operation information to the corresponding reservation stations while the associated instructions are being decoded. The speculative register file stores speculative register values corresponding to previously decoded instructions. The speculative register values are generated prior to execution of the previously decoded instructions. If the register operands included in the address operands of an instruction are stored in the speculative register file, then the memory operation may be passed through the corresponding reservation station to an address generation unit. The address generation unit generates the data address from the address operands and accesses a data cache while register operands corresponding to the instruction are requested from a register file and reorder buffer.

摘要翻译： 提供了包括地址生成单元，相应的保留站和推测寄存器文件的装置。 解码单元在对相关指令进行解码的同时向对应的保留站提供存储器操作信息。 推测寄存器文件存储与先前解码的指令相对应的推测寄存器值。 在执行先前解码的指令之前生成推测寄存器值。 如果包含在指令的地址操作数中的寄存器操作数存储在推测寄存器文件中，则存储器操作可以通过相应的保留站传递给地址生成单元。 地址生成单元从地址操作数生成数据地址，并访问数据高速缓存，同时从寄存器文件和重排序缓冲器请求与指令对应的寄存器操作数。

公开(公告)号：US5960467A

公开(公告)日：1999-09-28

申请号：US133340

申请日：1998-08-13

申请人： Rupaka Mahalingaiah ,  Thang M. Tran

发明人： Rupaka Mahalingaiah ,  Thang M. Tran

IPC分类号： G06F9/38 ,  G06F12/08 ,  G06F9/30

CPC分类号： G06F12/0875 ,  G06F9/3826 ,  G06F9/3832

摘要： An apparatus including address generation units, corresponding reservation stations, and a speculative register file is provided. Decode units provide memory operation information to the corresponding reservation stations while the associated instructions are being decoded. The speculative register file stores speculative register values corresponding to previously decoded instructions. The speculative register values are generated prior to execution of the previously decoded instructions. If the register operands included in the address operands of an instruction are stored in the speculative register file, then the memory operation may be passed through the corresponding reservation station to an address generation unit. The address generation unit generates the data address from the address operands and accesses a data cache while register operands corresponding to the instruction are requested from a register file and reorder buffer.

摘要翻译： 提供了包括地址生成单元，相应的保留站和推测寄存器文件的装置。 解码单元在对相关指令进行解码的同时向对应的保留站提供存储器操作信息。 推测寄存器文件存储与先前解码的指令相对应的推测寄存器值。 在执行先前解码的指令之前生成推测寄存器值。 如果包含在指令的地址操作数中的寄存器操作数存储在推测寄存器文件中，则存储器操作可以通过相应的保留站传递给地址生成单元。 地址生成单元从地址操作数生成数据地址，并访问数据高速缓存，同时从寄存器文件和重排序缓冲器请求与指令对应的寄存器操作数。