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1.发明授权Cache holding register for receiving instruction packets and for providing the instruction packets to a predecode unit and instruction cache 失效缓存保持寄存器，用于接收指令包，并将指令包提供给预解码单元和指令高速缓存
公开(公告)号：US5983321A
公开(公告)日：1999-11-09
申请号：US815567
申请日：1997-03-12
CPC分类号： G06F9/382 , G06F9/30036 , G06F9/30094 , G06F9/30101 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857
摘要： An instruction cache employing a cache holding register is provided. When a cache line of instruction bytes is fetched from main memory, the instruction bytes are temporarily stored into the cache holding register as they are received from main memory. The instruction bytes are predecoded as they are received from the main memory. If a predicted-taken branch instruction is encountered, the instruction fetch mechanism within the instruction cache begins fetching instructions from the target instruction path. This fetching may be initiated prior to receiving the complete cache line containing the predicted-taken branch instruction. As long as instruction fetches from the target instruction path continue to hit in the instruction cache, these instructions may be fetched and dispatched into a microprocessor employing the instruction cache. The remaining portion of the cache line of instruction bytes containing the predicted-taken branch instruction is received by the cache holding register. In order to reduce the number of ports employed upon the instruction bytes storage used to store cache lines of instructions, the cache holding register retains the cache line until an idle cycle occurs in the instruction bytes storage. The same port ordinarily used for fetching instructions is then used to store the cache line into the instruction bytes storage. In one embodiment, the instruction cache prefetches a succeeding cache line to the cache line which misses. A second cache holding register is employed for storing the prefetched cache line.
摘要翻译： 提供采用高速缓存保持寄存器的指令高速缓存器。 当从主存储器取出指令字节的高速缓存行时，指令字节从主存储器接收时临时存储到高速缓存保持寄存器中。 指令字节是从主存储器接收到的预解码的。 如果遇到预测的分支指令，则指令高速缓存内的指令获取机制开始从目标指令路径获取指令。 可以在接收到包含预测的分支指令的完整高速缓存行之前启动该获取。 只要从目标指令路径获取的指令继续命中指令高速缓存，可以将这些指令提取并分派到采用指令高速缓存的微处理器中。 由高速缓存保持寄存器接收包含预测的分支指令的指令字节的高速缓存行的剩余部分。 为了减少用于存储高速缓存行指令的指令字节存储器所使用的端口数量，高速缓存保持寄存器保持高速缓存行直到在指令字节存储器中发生空闲周期。 通常用于提取指令的相同端口用于将高速缓存行存储到指令字节存储器中。 在一个实施例中，指令高速缓存将后续的高速缓存行预取到丢失的高速缓存行。 采用第二高速缓存保存寄存器来存储预取的高速缓存行。
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2.发明授权Cache holding register for delayed update of a cache line into an instruction cache 失效缓存保持寄存器用于将高速缓存行的延迟更新延迟到指令高速缓存
公开(公告)号：US6076146A
公开(公告)日：2000-06-13
申请号：US310356
申请日：1999-05-12
CPC分类号： G06F9/382 , G06F9/30036 , G06F9/30094 , G06F9/30101 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3836 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857
摘要： An instruction cache employing a cache holding register is provided. When a cache line of instruction bytes is fetched from main memory, the instruction bytes are temporarily stored into the cache holding register as they are received from main memory. The instruction bytes are predecoded as they are received from the main memory. If a predicted-taken branch instruction is encountered, the instruction fetch mechanism within the instruction cache begins fetching instructions from the target instruction path. This fetching may be initiated prior to receiving the complete cache line containing the predicted-taken branch instruction. As long as instruction fetches from the target instruction path continue to hit in the instruction cache, these instructions may be fetched and dispatched into a microprocessor employing the instruction cache. The remaining portion of the cache line of instruction bytes containing the predicted-taken branch instruction is received by the cache holding register. In order to reduce the number of ports employed upon the instruction bytes storage used to store cache lines of instructions, the cache holding register retains the cache line until an idle cycle occurs in the instruction bytes storage. The same port ordinarily used for fetching instructions is then used to store the cache line into the instruction bytes storage. In one embodiment, the instruction cache prefetches a succeeding cache line to the cache line which misses. A second cache holding register is employed for storing the prefetched cache line.
摘要翻译： 提供采用高速缓存保持寄存器的指令高速缓存器。 当从主存储器取出指令字节的高速缓存行时，指令字节从主存储器接收时临时存储到高速缓存保持寄存器中。 指令字节是从主存储器接收到的预解码的。 如果遇到预测的分支指令，则指令高速缓存内的指令获取机制开始从目标指令路径获取指令。 可以在接收到包含预测的分支指令的完整高速缓存行之前启动该获取。 只要从目标指令路径获取的指令继续命中指令高速缓存，可以将这些指令提取并分派到采用指令高速缓存的微处理器中。 由高速缓存保持寄存器接收包含预测的分支指令的指令字节的高速缓存行的剩余部分。 为了减少用于存储高速缓存行指令的指令字节存储器所使用的端口数量，高速缓存保持寄存器保持高速缓存行直到在指令字节存储器中发生空闲周期。 通常用于提取指令的相同端口用于将高速缓存行存储到指令字节存储器中。 在一个实施例中，指令高速缓存将后续的高速缓存行预取到丢失的高速缓存行。 采用第二高速缓存保存寄存器来存储预取的高速缓存行。
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3.发明授权Predecoding technique for indicating locations of opcode bytes in variable byte-length instructions within a superscalar microprocessor 失效用于指示超标量微处理器内可变字节长度指令中操作码字节位置的预编码技术
公开(公告)号：US6049863A
公开(公告)日：2000-04-11
申请号：US873344
申请日：1997-06-11
CPC分类号： G06F9/382 , G06F9/30152 , G06F9/3017 , G06F9/3816 , G06F9/3853
摘要： A predecode unit is configured to predecode variable byte-length instructions prior to their storage within an instruction cache of a superscalar microprocessor. The predecode unit generates three predecode bits associated with each byte of instruction code: a "start" bit, an "end" bit, and a "functional" bit. The start bit is set if the associated byte is the first byte of the instruction. Similarly, the end bit is set if the byte is the last byte of the instruction. The functional bits convey information regarding the location of an opcode byte for a particular instruction as well as an indication of whether the instruction can be decoded directly by the decode logic of the processor or whether the instruction is executed by invoking a microcode procedure controlled by an MROM unit. For fast path instructions, the functional bit is set for each prefix byte included in the instruction, and cleared for other bytes. For MROM instructions, the functional bit is cleared for each prefix byte and is set for other bytes. The type of instruction (either fast path or MROM) may thus be determined by examining the functional bit corresponding to the end byte of the instruction. If that functional bit is clear, the instruction is a fast path instruction. Conversely, if that functional bit is set, the instruction is an NMOM instruction. After an MROM instruction is identified, the functional bits for the instruction may be inverted. Subsequently, the opcode for both fast path and MROM instructions may readily be located (by the alignment logic) by determining the first byte within the instruction that has a cleared functional bit.
摘要翻译： 预解码单元被配置为在可变字节长度指令被存储在超标量微处理器的指令高速缓存之前预先解码。 预解码单元产生与指令代码的每个字节相关联的三个预解码位：“起始”位，“结束”位和“功能”位。 如果相关字节是指令的第一个字节，则起始位置1。 类似地，如果字节是指令的最后一个字节，则结束位置1。 功能位传送关于特定指令的操作码字节的位置的信息以及指令是否可以由处理器的解码逻辑直接解码，或者指令是否通过调用由控制的微代码过程来执行 MROM单位。 对于快速通道指令，为指令中包含的每个前缀字节设置功能位，并为其他字节清零。 对于MROM指令，每个前缀字节清除功能位，并为其他字节设置。 因此，可以通过检查对应于指令的结束字节的功能位来确定指令的类型（快速路径或MROM）。 如果该功能位清零，该指令是快速路径指令。 相反，如果该功能位被置位，则指令是NMOM指令。 识别出MROM指令后，指令的功能位可能会反转。 随后，快速路径和MROM指令的操作码可以通过确定具有清除的功能位的指令内的第一个字节来容易地（由对准逻辑）定位。
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4.发明授权公开(公告)号：US06253316B1
公开(公告)日：2001-06-26
申请号：US09438963
申请日：1999-11-12
IPC分类号： G06F944
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3844
摘要： A branch prediction unit stores a set of branch prediction history bits and branch selectors corresponding to each of a group of contiguous instruction bytes stored in an instruction cache. While only one bit is used to represent branch prediction history, three distinct states are represented in conjunction with the absence of a branch prediction. This provides for the storage of fewer bits, while maintaining a high degree of branch prediction accuracy. Each branch selector identifies the branch prediction to be selected if a fetch address corresponding to that branch selector is presented. In order to minimize the number of branch selectors stored for a group of contiguous instruction bytes, the group is divided into multiple byte ranges. The largest byte range may include a number of bytes comprising the shortest branch instruction in the instruction set (exclusive of the return instruction). For example, the shortest branch instruction may be two bytes in one embodiment. Therefore, the largest byte range is two bytes in the example. Since the branch selectors as a group change value (i.e. indicate a different branch instruction) only at the end byte of a predicted-taken branch instruction, fewer branch selectors may be stored than the number of bytes within the group.
摘要翻译： 分支预测单元存储对应于存储在指令高速缓存中的一组连续指令字节中的每一个分支预测历史位和分支选择器的集合。 虽然仅使用一个比特来表示分支预测历史，但是与不存在分支预测一起表示三个不同的状态。 这提供了存储较少位，同时保持高度的分支预测精度。 如果呈现与该分支选择器相对应的获取地址，则每个分支选择器识别要选择的分支预测。 为了最小化一组连续指令字节存储的分支选择器的数量，该组被划分为多个字节范围。 最大字节范围可以包括包括指令集中的最短分支指令（不包括返回指令）的字节数。 例如，在一个实施例中，最短分支指令可以是两个字节。 因此，在该示例中，最大字节范围是两个字节。 由于分支选择器作为组改变值（即指示不同的分支指令）仅在预测的分支指令的结束字节处，所以可以存储比组内的字节数少的分支选择器。
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公开(公告)号：US5954816A
公开(公告)日：1999-09-21
申请号：US972988
申请日：1997-11-19
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/30054 , G06F9/3806
摘要： A branch prediction unit includes a branch prediction entry corresponding to a group of contiguous instruction bytes. The branch prediction entry stores branch predictions corresponding to branch instructions within the group of contiguous instruction bytes. Additionally, the branch prediction entry stores a set of branch selectors corresponding to the group of contiguous instruction bytes. The branch selectors identify which branch prediction is to be selected if the corresponding byte (or bytes) is selected by the offset portion of the fetch address. Still further, a predicted branch selector is stored. The predicted branch selector is used to select a branch prediction for forming the fetch address. In parallel, a selected branch selector is selected from the set of branch selectors. The predicted branch selector is verified using the selected branch selector. If the selected branch selector and the predicted branch selector mismatch, the correct branch prediction is generated and the predicted branch selector is updated to indicate the selected branch selector.
摘要翻译： 分支预测单元包括对应于一组相邻指令字节的分支预测条目。 分支预测条目存储对应于连续指令字节组内的分支指令的分支预测。 此外，分支预测条目存储对应于该组连续指令字节的一组分支选择器。 如果通过提取地址的偏移部分选择了相应的字节（或字节），则分支选择器识别要选择哪个分支预测。 此外，存储预测分支选择器。 预测分支选择器用于选择用于形成取出地址的分支预测。 并行地，从分支选择器组中选择选择的分支选择器。 使用所选择的分支选择器验证预测分支选择器。 如果所选择的分支选择器和预测分支选择器不匹配，则生成正确的分支预测，并且更新预测分支选择器以指示所选择的分支选择器。
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6.发明授权Reduced size storage apparatus for storing cache-line-related data in a high frequency microprocessor 失效用于在高频微处理器中存储高速缓存线相关数据的减小尺寸的存储装置
公开(公告)号：US6016545A
公开(公告)日：2000-01-18
申请号：US991694
申请日：1997-12-16
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F9/3844
摘要： A microprocessor stores cache-line-related data (e.g. branch predictions or predecode data, in the illustrated embodiments) in a storage which includes fewer storage locations than the number of cache lines in the instruction cache. Each storage location in the storage is mappable to multiple cache lines, any one of which can be associated with the data stored in the storage location. The storage may thereby be smaller than a storage which provides an equal number of storage locations as the number of cache lines in the instruction cache. Access time to the storage may be reduced, therefore providing for a higher frequency implementation. Still further, semiconductor substrate area occupied by the storage may be decreased. In one embodiment, the storage is indexed by a subset of the index bits used to index the instruction cache. The subset comprises the least significant bits of the cache index. In other words, the cache lines which share a particular storage location within the storage differ in the most significant cache index bits. Therefore, code which exhibits spatial locality may experience little conflict for the storage locations.
摘要翻译： 微处理器将包含比指令高速缓存中的高速缓存行的数量更少的存储位置的存储器中的高速缓存线相关数据（例如在所示实施例中的分支预测或预解码数据）存储在存储器中。 存储器中的每个存储位置可映射到多个高速缓存行，其中任何一个可以与存储在存储位置中的数据相关联。 因此，存储器可以小于提供与指令高速缓存中的高速缓存行数相同数量的存储位置的存储器。 可能减少对存储器的访问时间，因此提供更高频率的实现。 此外，可以减少由存储器占据的半导体衬底区域。 在一个实施例中，存储器被用于索引指令高速缓存的索引位的子集索引。 该子集包括高速缓存索引的最低有效位。 换句话说，在存储器中共享特定存储位置的高速缓存行在最重要的高速缓存索引位中不同。 因此，展示空间局部性的代码可能对存储位置的冲突很小。
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7.发明授权Array having an update circuit for updating a storage location with a value stored in another storage location 失效阵列具有用于利用存储在另一存储位置中的值来更新存储位置的更新电路
公开(公告)号：US5687110A
公开(公告)日：1997-11-11
申请号：US603802
申请日：1996-02-20
申请人： Thang M. Tran , Andrew McBride
发明人： Thang M. Tran , Andrew McBride
CPC分类号： G06F9/3844 , G06F9/3857 , G06F9/3863
摘要： A memory including first storage circuits for storing first values and second storages circuit for storing second values is provided. The first value may be retired branch prediction information, while the second value may be speculative branch prediction information. The speculative branch prediction information is updated when the corresponding instructions are fetched, and the retired branch prediction value is updated when the corresponding branch instruction is retired. The speculative branch prediction information is used to form branch predictions. Therefore, the speculatively fetched and executed branches influence subsequent branch predictions. Upon detection of a mispredicted branch or an instruction which causes an exception, the speculative branch prediction information is updated to the corresponding retired branch prediction information. An update circuit is coupled between the first and second storage circuits for transmitting the updated information upon assertion of a control signal. The control signal may be asserted to cause the update of each speculative branch prediction by the corresponding retired branch prediction. The updates occur substantially simultaneously, restoring any corruption to speculative branch predictions due to speculatively fetched branch instructions which were flushed from the instruction processing pipeline. Although discussed herein in terms of a branch prediction array, the memory may be adapted to many other applications.
摘要翻译： 提供了包括用于存储第一值的第一存储电路和用于存储第二值的第二存储电路的存储器。 第一值可以是退休分支预测信息，而第二值可以是推测性分支预测信息。 当对应的指令被取出时，推测分支预测信息被更新，并且当对应的分支指令退出时，退出的分支预测值被更新。 推测分支预测信息用于形成分支预测。 因此，推测取得和执行的分支影响后续的分支预测。 在检测到错误的分支或引起异常的指令时，将推测性分支预测信息更新为相应的退出分支预测信息。 更新电路耦合在第一和第二存储电路之间，用于在断言控制信号时发送更新的信息。 控制信号可以被断言，以通过相应的退役分支预测使每个推测分支预测的更新。 这些更新基本上同时发生，由于从指令处理流水线刷新的推测性获取的分支指令，将任何损坏恢复到推测性分支预测。 尽管这里在分支预测阵列方面进行了讨论，但存储器可以适用于许多其他应用。
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公开(公告)号：US07043679B1
公开(公告)日：2006-05-09
申请号：US10180207
申请日：2002-06-27
IPC分类号： G11C29/00
CPC分类号： G06F11/106 , G06F11/1064
摘要： An apparatus including circuitry configured to detect and correct an ECC error in a non-targeted portion of a load access to a first data in a memory. An ECC error check circuit is configured to convey a first indication in response to detecting an error in a non-targeted first portion of the first data. A microcode unit is coupled to receive the first indication that the ECC check circuit has detected the ECC error and in response to the indication dispatch a first microcode routine stored by the microcode unit. The first microcode routine includes instructions which, when executed, correct the ECC error in the first portion. Correction of the error in the first portion does not include cancellation of data corresponding to the load access.
摘要翻译： 一种装置，包括被配置为检测和校正存储器中的第一数据的负载访问的非目标部分中的ECC错误的电路。 ECC错误检查电路被配置为响应于检测到第一数据的非目标第一部分中的错误而传达第一指示。 微代码单元被耦合以接收ECC检查电路已经检测到ECC错误的第一指示，并且响应于指示分派由微代码单元存储的第一微代码例程。 第一微代码例程包括指令，当被执行时，该指令校正第一部分中的ECC错误。 纠正第一部分中的错误不包括取消与负载访问相对应的数据。
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公开(公告)号：US20170114695A1
公开(公告)日：2017-04-27
申请号：US14924399
申请日：2015-10-27
申请人： Jordan Mosher , Nishant Singh , Andrew McBride
发明人： Jordan Mosher , Nishant Singh , Andrew McBride
CPC分类号： F01N11/00 , B01D46/44 , F01N2550/04 , F01N2900/1606 , G01M15/102 , Y02T10/47
摘要： A system for estimating an amount of soot in an exhaust particulate filter includes a delta P soot load estimate generator configured to generate a first soot load estimate as a function of a pressure drop and a mass flow of exhaust. The system further includes a model estimate generator configured to generate a second soot load estimate as a function of a modeled engine performance. A trust factor generator is configured to determine a trust factor signal as a function of at least one engine operating characteristic, and a decision generator is configured to determine whether to use the first soot load estimate or the second soot load estimate as a function of the trust factor signal.
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公开(公告)号：US10392998B2
公开(公告)日：2019-08-27
申请号：US14924399
申请日：2015-10-27
申请人： Jordan Mosher , Nishant Singh , Andrew McBride
发明人： Jordan Mosher , Nishant Singh , Andrew McBride
摘要： A system for estimating an amount of soot in an exhaust particulate filter includes a delta P soot load estimate generator configured to generate a first soot load estimate as a function of a pressure drop and a mass flow of exhaust. The system further includes a model estimate generator configured to generate a second soot load estimate as a function of a modeled engine performance. A trust factor generator is configured to determine a trust factor signal as a function of at least one engine operating characteristic, and a decision generator is configured to determine whether to use the first soot load estimate or the second soot load estimate as a function of the trust factor signal.
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