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公开(公告)号：US07330936B2
公开(公告)日：2008-02-12
申请号：US11109163
申请日：2005-04-19
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F12/1054 , G06F2212/1028 , Y02D10/13
摘要： A system and method for power efficient memory caching. Some illustrative embodiments may include a system comprising: a hash address generator coupled to an address bus (the hash address generator converts a bus address present on the address bus into a current hashed address); a cache memory coupled to the address bus (the cache memory comprises a tag stored in one of a plurality of tag cache ways and data stored in one of a plurality of data cache ways); and a hash memory coupled to the address bus (the hash memory comprises a saved hashed address, the saved hashed address associated with the data and the tag). Less than all of the plurality of tag cache ways are enabled when the current hashed address matches the saved hashed addresses. An enabled tag cache way comprises the tag.
摘要翻译： 一种用于高效内存缓存的系统和方法。 一些说明性实施例可以包括：系统，其包括：耦合到地址总线的散列地址发生器（所述散列地址生成器将存在于所述地址总线上的总线地址转换为当前散列的地址）; 耦合到所述地址总线的高速缓存存储器（所述高速缓冲存储器包括存储在多个标签高速缓存路径中的一个中的标签和存储在多个数据高速缓存路径之一中的数据）; 以及耦合到地址总线的散列存储器（散列存储器包括保存的散列地址，与数据和标签相关联的保存的散列地址）。 当当前散列的地址与保存的散列地址匹配时，小于所有多个标签高速缓存方式被启用。 启用的标签缓存方式包括标签。
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公开(公告)号：US07330964B2
公开(公告)日：2008-02-12
申请号：US11273493
申请日：2005-11-14
IPC分类号： G06F9/40
CPC分类号： G06F9/381 , G06F9/30036 , G06F9/325 , G06F9/3885 , G06F9/3887
摘要： An apparatus comprising detection logic configured to detect a loop among a set of instructions, the loop comprising one or more instructions of a first type of instruction and a second type of instruction and a co-processor configured to execute the loop detected by the detection logic, the co-processor comprising an instruction queue. The apparatus further comprises fetch logic configured to fetch instructions; decode logic configured to determine instruction type; a processor configured to execute the loop detected by the detection logic, wherein the loop comprises one or more instructions of the first type of instruction, and an execution unit configured to execute the loop detected by the detection logic.
摘要翻译： 一种装置，包括被配置为检测一组指令中的循环的检测逻辑，该循环包括第一类型的指令和第二类型的指令的一个或多个指令，以及被配置为执行由检测逻辑检测到的循环的协处理器 协处理器包括指令队列。 所述设备还包括被配置为获取指令的提取逻辑; 解码逻辑配置为确定指令类型; 被配置为执行由检测逻辑检测到的循环的处理器，其中所述循环包括所述第一类型的指令的一个或多个指令，以及被配置为执行由所述检测逻辑检测到的所述循环的执行单元。
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公开(公告)号：US06249862B1
公开(公告)日：2001-06-19
申请号：US09715467
申请日：2000-11-15
IPC分类号： G06F938
CPC分类号： G06F9/30036 , G06F9/30112 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3861
摘要： A dependency table stores a reorder buffer tag for each register. The stored reorder buffer tag corresponds to the last of the instructions within the reorder buffer (in program order) to update the register. Otherwise, the dependency table indicates that the value stored in the register is valid. When operand fetch is performed for a set of concurrently decoded instructions, dependency checking is performed including checking for dependencies between the set of concurrently decoded instructions as well as accessing the dependency table to select the reorder buffer tag stored therein. Either the reorder buffer tag of one of the concurrently decoded instructions, the reorder buffer tag stored in the dependency table, the instruction result corresponding to the stored reorder buffer tag, or the value from the register itself is forwarded as the source operand for the instruction. Information from the comparators and the information stored in the dependency table is sufficient to select which value is forwarded. Additionally, the dependency table stores the width of the register being updated. Prior to forwarding the reorder buffer tag stored within the dependency table, the width stored therein is compared to the width of the source operand being requested. If a narrow-to-wide dependency is detected the instruction is stalled until the instruction indicated in the dependency table retires. Still further, the dependency table recovers from branch mispredictions and exceptions by redispatching the instructions into the dependency table.
摘要翻译： 依赖关系表存储每个寄存器的重排序缓冲区标签。 存储的重排序缓冲器标签对应于重新排序缓冲器中的最后一个指令（以程序顺序）来更新寄存器。 否则，依赖关系表表示存储在寄存器中的值有效。 当对一组并行解码的指令执行操作数提取时，执行依赖性检查，包括检查所述一组并行解码指令之间的依赖性以及访问依赖关系表以选择其中存储的重排序缓冲器标签。 同时解码的指令之一的重排序缓冲器标签，存储在依赖关系表中的重排序缓冲器标签，与存储的重排序缓冲器标签相对应的指令结果或来自寄存器本身的值被转发作为指令的源操作数 。 来自比较器的信息和存储在依赖关系表中的信息足以选择转发哪个值。 另外，依赖关系表存储正被更新的寄存器的宽度。 在转发存储在依赖关系表内的重新排序缓冲器标签之前，将其中存储的宽度与所请求的源操作数的宽度进行比较。 如果检测到窄到宽的依赖关系，则指令停止，直到依赖关系表中指示的指令退出。 此外，依赖关系表通过将指令重新分配到依赖关系表中，从分支错误预测和异常中恢复。
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公开(公告)号：US06209084B1
公开(公告)日：2001-03-27
申请号：US09566216
申请日：2000-05-05
IPC分类号： G06F1500
CPC分类号： G06F9/30036 , G06F9/30112 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3861
摘要： A dependency table stores a reorder buffer tag for each register. When operand fetch is performed for a set of concurrently decoded instructions, dependency checking is performed including checking for dependencies between the set of concurrently decoded instructions as well as accessing the dependency table to select the reorder buffer tag stored therein. Either the reorder buffer tag of one of the concurrently decoded instructions, the reorder buffer tag stored in the dependency table, the instruction result corresponding to the stored reorder buffer tag, or the value from the register itself is forwarded as the source operand for the instruction. The dependency table stores the width of the register being updated. Prior to forwarding the reorder buffer tag stored within the dependency table, the width stored therein is compared to the width of the source operand being requested. If a narrow-to-wide dependency is detected the instruction is stalled until the instruction indicated in the dependency table retires.
摘要翻译： 依赖关系表存储每个寄存器的重排序缓冲区标签。 当对一组并行解码的指令执行操作数提取时，执行依赖性检查，包括检查所述一组并行解码指令之间的依赖性以及访问依赖关系表以选择其中存储的重排序缓冲器标签。 同时解码的指令之一的重排序缓冲器标签，存储在依赖关系表中的重排序缓冲器标签，与存储的重排序缓冲器标签相对应的指令结果或来自寄存器本身的值被转发作为指令的源操作数 。 依赖表存储要更新的寄存器的宽度。 在转发存储在依赖关系表内的重新排序缓冲器标签之前，将其中存储的宽度与所请求的源操作数的宽度进行比较。 如果检测到窄到宽的依赖关系，则指令停止，直到依赖关系表中指示的指令退出。
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公开(公告)号：US07237065B2
公开(公告)日：2007-06-26
申请号：US11136169
申请日：2005-05-24
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F9/30043 , G06F9/3824 , G06F9/3885 , G06F12/0811 , G06F12/0888 , G06F2212/1021
摘要： A processor comprises decode logic that determines an instruction type for each instruction fetched, a first level cache, a second level cache coupled to the first level cache, and control logic operatively coupled to the first and second level caches. The control logic preferably causes cache linefills to be performed to the first level cache upon cache misses for a first type of instruction, but precludes linefills from being performed to the first level cache for a second type of instruction.
摘要翻译： 处理器包括解码逻辑，其确定所取得的每条指令的指令类型，第一级高速缓存，耦合到第一级高速缓存的第二级高速缓存以及可操作地耦合到第一和第二级高速缓存的控制逻辑。 控制逻辑优选地在对于第一类型的指令的高速缓存未命中时，对第一级高速缓存执行高速缓存行填充，但是排除了对于第二类型的指令而对第一级高速缓存执行排线。
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公开(公告)号：US6108769A
公开(公告)日：2000-08-22
申请号：US649247
申请日：1996-05-17
CPC分类号： G06F9/30036 , G06F9/30112 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3861
摘要： A dependency table stores a reorder buffer tag for each register. The stored reorder buffer tag corresponds to the last of the instructions within the reorder buffer (in program order) to update the register. Otherwise, the dependency table indicates that the value stored in the register is valid. When operand fetch is performed for a set of concurrently decoded instructions, dependency checking is performed including checking for dependencies between the set of concurrently decoded instructions as well as accessing the dependency table to select the reorder buffer tag stored therein. Either the reorder buffer tag of one of the concurrently decoded instructions, the reorder buffer tag stored in the dependency table, the instruction result corresponding to the stored reorder buffer tag, or the value from the register itself is forwarded as the source operand for the instruction. Information from the comparators and the information stored in the dependency table is sufficient to select which value is forwarded. Additionally, the dependency table stores the width of the register being updated. Prior to forwarding the reorder buffer tag stored within the dependency table, the width stored therein is compared to the width of the source operand being requested. If a narrow-to-wide dependency is detected the instruction is stalled until the instruction indicated in the dependency table retires. Still further, the dependency table recovers from branch mispredictions and exceptions by redispatching the instructions into the dependency table.
摘要翻译： 依赖关系表存储每个寄存器的重排序缓冲区标签。 存储的重排序缓冲器标签对应于重新排序缓冲器中的最后一个指令（以程序顺序）来更新寄存器。 否则，依赖关系表表示存储在寄存器中的值有效。 当对一组并行解码的指令执行操作数提取时，执行依赖性检查，包括检查所述一组并行解码指令之间的依赖性以及访问依赖关系表以选择其中存储的重排序缓冲器标签。 同时解码的指令之一的重排序缓冲器标签，存储在依赖关系表中的重排序缓冲器标签，与存储的重排序缓冲器标签相对应的指令结果或来自寄存器本身的值被转发作为指令的源操作数 。 来自比较器的信息和存储在依赖关系表中的信息足以选择转发哪个值。 另外，依赖关系表存储正被更新的寄存器的宽度。 在转发存储在依赖关系表内的重新排序缓冲器标签之前，将其中存储的宽度与所请求的源操作数的宽度进行比较。 如果检测到窄到宽的依赖关系，则指令停止，直到依赖关系表中指示的指令退出。 此外，依赖关系表通过将指令重新分配到依赖关系表中，从分支错误预测和异常中恢复。
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7.发明授权System and method for high performance, power efficient store buffer forwarding 有权用于高性能，高效能存储缓冲区转发的系统和方法公开(公告)号：US08775740B2
公开(公告)日：2014-07-08
申请号：US11214501
申请日：2005-08-30
IPC分类号： G06F12/08
CPC分类号： G06F12/0864 , G06F9/3824 , G06F9/3826 , G06F9/3834 , G06F9/3842 , G06F9/3861 , G06F12/0855 , G06F2212/6032 , G06F2212/6082 , Y02D10/13
摘要： The present disclosure describes a system and method for high performance, power efficient store buffer forwarding. Some illustrative embodiments may include a system, comprising: a processor coupled to an address bus; a cache memory that couples to the address bus and comprises cache data (the cache memory divided into a plurality of ways); and a store buffer that couples to the address bus, and comprises store buffer data, a store buffer way and a store buffer index. The processor selects the store buffer data for use by a data load operation if a selected way of the plurality of ways matches the store buffer way, and if at least part of the bus address matches the store buffer index.
摘要翻译： 本公开描述了用于高性能，功率效率的存储缓冲器转发的系统和方法。 一些说明性实施例可以包括系统，包括：耦合到地址总线的处理器; 缓存存储器，其耦合到地址总线并且包括高速缓存数据（被分成多个方式的高速缓冲存储器）; 以及存储缓冲器，其耦合到地址总线，并且包括存储缓冲器数据，存储缓冲器方式和存储缓冲器索引。 如果多个方式的选定方式与存储缓冲器方式相匹配，并且总线地址的至少一部分与存储缓冲器索引匹配，则处理器选择存储缓冲器数据以供数据加载操作使用。
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8.发明授权Load/store unit implementing non-blocking loads for a superscalar microprocessor and method of selecting loads in a non-blocking fashion from a load/store buffer 失效加载/存储单元实现超标量微处理器的非阻塞负载以及以非阻塞方式从加载/存储缓冲区中选择负载的方法
公开(公告)号：US5802588A
公开(公告)日：1998-09-01
申请号：US858583
申请日：1997-05-19
CPC分类号： G06F12/0859 , G06F9/3824 , G06F9/3834
摘要： A load/store buffer is provided which allows both load memory operations and store memory operations to be stored within it. Memory operations are selected from the load/store buffer for access to the data cache, including cases where the memory operation selected is subsequent in program order to a memory operation which is known to miss the data cache and is stored in the buffer. In this way, other memory operations that may be waiting for an opportunity to access the data cache may make such accesses, while the memory operations that have missed await an opportunity to make a main memory request. Memory operations that have missed are indicated by a miss bit being set, so that the mechanism which selects memory operations to access the data cache may ignore them until they become non-speculative.
摘要翻译： 提供了一个加载/存储缓冲区，允许加载存储器操作和存储存储器操作存储在其中。 从加载/存储缓冲器中选择存储器操作以访问数据高速缓存，包括所选择的存储器操作以程序顺序连续到已知丢失数据高速缓存并存储在缓冲器中的存储器操作的情况。 以这种方式，可能正在等待访问数据高速缓存的机会的其他存储器操作可以进行这样的访问，而错过的存储器操作等待有机会进行主存储器请求。 错过的存储器操作由设置的未命中位指示，从而选择存储器操作以访问数据高速缓存的机制可以忽略它们，直到它们变得不投机。
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