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公开(公告)号：US07532187B2
公开(公告)日：2009-05-12
申请号：US11184699
申请日：2005-07-18
CPC分类号： G09G3/20 , G09G3/3208 , G09G3/3659 , G09G2300/08 , G09G2310/0262 , H01L29/78648
摘要： A dual-gate thin-film transistor (DG-TFT) voltage storage circuit is provided. The circuit includes a voltage storage element, a DG-TFT having a first source/drain (S/D) connected to a data line, a top gate connected to a first gate line, a second S/D region connected to the voltage storage element, and a bottom gate connected to a bias line. In one aspect, the circuit further includes a voltage shifter having an input connected to the first gate line and an output to supply a bias voltage on the bias line. Examples of a voltage storage element include a capacitor, a liquid crystal (LC) pixel, and a light emitting diode (LED) pixel.
摘要翻译： 提供了双栅极薄膜晶体管（DG-TFT）电压存储电路。 电路包括电压存储元件，具有连接到数据线的第一源极/漏极（S / D）的DG-TFT，连接到第一栅极线的顶栅极，连接到电压存储器的第二S / D区域 元件和连接到偏置线的底栅。 在一个方面，电路还包括具有连接到第一栅极线的输入的电压移位器和用于在偏置线上提供偏置电压的输出。 电压存储元件的实例包括电容器，液晶（LC）像素和发光二极管（LED）像素。
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公开(公告)号：US08236631B2
公开(公告)日：2012-08-07
申请号：US12644061
申请日：2009-12-22
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译： 提供了一个四晶体管施密特触发器。 施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极， 背栅极和源极/漏极区域。 （常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。 （传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。
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公开(公告)号：US20100117704A1
公开(公告)日：2010-05-13
申请号：US12644061
申请日：2009-12-22
IPC分类号： H03K3/00
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译： 提供了一个四晶体管施密特触发器。 施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极， 背栅极和源极/漏极区域。 （常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。 （传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。
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公开(公告)号：US07659586B2
公开(公告)日：2010-02-09
申请号：US12142602
申请日：2008-06-19
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译： 提供了一个四晶体管施密特触发器。 施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极， 背栅极和源极/漏极区域。 （常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。 （传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。
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公开(公告)号：US20080272816A1
公开(公告)日：2008-11-06
申请号：US12142602
申请日：2008-06-19
IPC分类号： H03K3/00
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译： 提供了一个四晶体管施密特触发器。 施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极， 背栅极和源极/漏极区域。 （常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。 （传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。
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公开(公告)号：US07407843B2
公开(公告)日：2008-08-05
申请号：US11408220
申请日：2006-04-20
CPC分类号： H03K3/3565 , H01L29/78624 , H01L29/78642 , H01L29/78648
摘要： A four-transistor Schmitt trigger inverter is provided. The Schmitt trigger inverter is made from an n-channel MOS (NMOS) dual-gate thin-film transistor (DG-TFT) and a p-channel MOS (PMOS) DG-TFT, both DG-TFTs having a top gate, a back gate, and source/drain regions. A (conventional) NMOS TFT has a gate connected to an NMOS DG-TFT first S/D region and a PMOS DG-TFT first S/D region. The NMOS TFT also has a first S/D region connected to the NMOS DG-TFT back gate and the PMOS DG-TFT back gate. A (conventional) PMOS TFT has a gate connected to the NMOS TFT gate, and a first S/D region connected to the NMOS TFT first S/D region.
摘要翻译： 提供了一个四晶体管施密特触发器。 施密特触发逆变器由n沟道MOS（NMOS）双栅极薄膜晶体管（DG-TFT）和p沟道MOS（PMOS）DG-TFT制成，两个DG-TFT都具有顶栅极， 背栅极和源极/漏极区域。 （常规）NMOS TFT具有连接到NMOS DG-TFT第一S / D区和PMOS DG-TFT第一S / D区的栅极。 NMOS TFT还具有连接到NMOS DG-TFT背栅和PMOS DG-TFT后栅的第一S / D区。 （传统）PMOS TFT具有连接到NMOS TFT栅极的栅极和连接到NMOS TFT第一S / D区域的第一S / D区域。
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公开(公告)号：US20090250700A1
公开(公告)日：2009-10-08
申请号：US12099756
申请日：2008-04-08
IPC分类号： H01L29/786 , H01L21/336 , H01L29/76
CPC分类号： H01L29/78696 , H01L21/02532 , H01L21/02686 , H01L27/1285 , H01L29/66757 , H01L29/66772 , H01L29/785
摘要： A transistor with crystalline semiconductor stripes and an associated fabrication process are provided. The method provides a substrate, and deposits a semiconductor layer overlying the substrate. The semiconductor layer is irradiated using a scanning step-and-repeat laser annealing process, which agglomerates portions of the semiconductor layer. In response to cooling agglomerated semiconductor material, a transistor active semiconductor region is formed including a plurality of crystalline semiconductor stripes oriented along parallel axes. In one aspect, a channel region is formed from the plurality of oriented crystalline semiconductor stripes, and the method forms a gate dielectric overlying the channel region, with a gate electrode overlying the gate dielectric. In another aspect, forming the transistor active semiconductor region includes forming source, drain, and channel regions from the plurality of oriented crystalline semiconductor stripes.
摘要翻译： 提供具有晶体半导体条纹和相关制造工艺的晶体管。 该方法提供衬底，并且沉积覆盖衬底的半导体层。 使用扫描分步重复激光退火工艺照射半导体层，其使半导体层的部分凝聚。 响应于冷却聚集的半导体材料，形成包括沿着平行轴定向的多个晶体半导体条纹的晶体管有源半导体区域。 在一个方面，由多个取向结晶半导体条形成沟道区，该方法形成覆盖沟道区的栅极电介质，栅电极覆盖栅电介质。 在另一方面，形成晶体管有源半导体区域包括从多个取向晶体半导体条形成源极，漏极和沟道区域。
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公开(公告)号：US20090250791A1
公开(公告)日：2009-10-08
申请号：US12099744
申请日：2008-04-08
CPC分类号： H01L29/66757 , H01L21/02532 , H01L21/02609 , H01L21/02686 , H01L29/78696
摘要： Crystalline semiconductor stripes and an associated fabrication process are provided. The method provides an insulator substrate, and deposits a semiconductor layer overlying the insulator substrate. The semiconductor layer is irradiated using a scanning step-and-repeat laser annealing process, which agglomerates portions of the semiconductor layer. In response to cooling agglomerated semiconductor material, oriented crystalline semiconductor stripes are formed on the insulator substrate. The crystalline semiconductor stripes are aligned approximately with a straight line stripe axis overlying a top surface of the insulating substrate. Each crystalline semiconductor stripe includes a plurality of consecutive ring segments aligned with the stripe axis. The rings segments have a width about equal to the laser annealing process step distance. The crystalline semiconductor stripes typically have a top surface shape of a truncated cylinder or a parabolic cross section.
摘要翻译： 提供了晶体半导体条纹和相关联的制造工艺。 该方法提供绝缘体衬底，并且沉积覆盖绝缘体衬底的半导体层。 使用扫描分步重复激光退火工艺照射半导体层，其使半导体层的部分凝聚。 响应于冷却聚集的半导体材料，在绝缘体基板上形成取向的结晶半导体条纹。 晶体半导体条纹大约与覆盖在绝缘基板的顶表面上的直线条纹轴对准。 每个晶体半导体条纹包括与条纹轴对准的多个连续的环段。 环段具有大约等于激光退火工艺步距的宽度。 晶体半导体条纹通常具有截顶圆柱体的顶表面形状或抛物线截面。
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公开(公告)号：US20090078940A1
公开(公告)日：2009-03-26
申请号：US11904133
申请日：2007-09-26
CPC分类号： H01L29/78672 , H01L27/1277 , H01L27/1285 , H01L29/6675 , H01L29/66757 , H01L29/78603 , H01L29/78648 , H01L29/78675
摘要： A structure with location-controlled crystallization of an active semiconductor film using a crystal seed has been provided, along with an associated fabrication method. The method forms a first semiconductor film overlying a substrate having a crystallographic orientation. Typically, the structure is polycrystalline or single-crystal. The first semiconductor film is selectively etched, forming a seed region. An insulator is formed with an opening, exposing the seed region. An amorphous second semiconductor film is formed over the insulator layer. The second semiconductor film is laser annealed, partially melting the seed region. Crystal grains are laterally grown in the second semiconductor film having the same crystallographic orientation as the seed region. In TFT fabrication an etching is typically performed to remove the second semiconductor film overlying the seed region, and a transistor active region is formed in the remaining second semiconductor film.
摘要翻译： 已经提供了使用晶种的有源半导体膜的位置控制结晶的结构，以及相关的制造方法。 该方法形成了覆盖具有晶体取向的衬底的第一半导体膜。 通常，该结构是多晶或单晶。 选择性地蚀刻第一半导体膜，形成种子区域。 绝缘体形成有开口，暴露种子区域。 在绝缘体层上方形成无定形的第二半导体膜。 第二半导体膜被激光退火，部分熔化种子区域。 在具有与种子区域相同的晶体取向的第二半导体膜中横向生长晶粒。 在TFT制造中，通常进行蚀刻以去除覆盖种子区域的第二半导体膜，并且在剩余的第二半导体膜中形成晶体管有源区。
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公开(公告)号：US20140198072A1
公开(公告)日：2014-07-17
申请号：US13740043
申请日：2013-01-11
IPC分类号： G06F3/044
CPC分类号： G06F3/044 , G06F3/0412 , G06F3/043
摘要： A video display is provided with a planar piezoelectric transmitter to transmit ultrasound signals, and a display panel including a plurality of pixels. Each pixel has a data interface to accept a video signal with a variable voltage associated with a range of light intensity values, and to supply a touch signal with a variable voltage derived from a range of reflected ultrasound signal energies. Each pixel is made up of a light device to supply light with an intensity responsive to the video signal voltage, and a storage capacitor to maintain a video signal voltage between refresh cycles. A piezoelectric transducer accepts a reflected ultrasound signal energy and maintains a touch signal voltage between refresh cycles. In one aspect, the storage capacitor and the piezoelectric transducer are the same device. The light device may be a liquid crystal (LC) layer or a light emitting diode.
摘要翻译： 视频显示器设置有用于传输超声波信号的平面压电发射器，以及包括多个像素的显示面板。 每个像素具有接收具有与一定范围的光强度值相关联的可变电压的视频信号的数据接口，并且提供具有从反射的超声信号能量的范围导出的可变电压的触摸信号。 每个像素由光装置组成，以响应于视频信号电压的强度提供光，以及存储电容器，用于在刷新周期之间维持视频信号电压。 压电传感器接受反射的超声信号能量并在刷新周期之间保持触摸信号电压。 一方面，存储电容器和压电换能器是相同的装置。 光装置可以是液晶（LC）层或发光二极管。
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