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1.发明授权Methods and apparatus for saving conditions prior to a reset for post reset evaluation 有权用于在复位后复位评估时保存条件的方法和装置公开(公告)号：US08880860B2
公开(公告)日：2014-11-04
申请号：US13309623
申请日：2011-12-02
IPC分类号： G06F15/177
CPC分类号： G06F11/1441
摘要： A processor reset control circuit is configured to automatically capture a pre-reset value of processor information stored in one or more hardware registers, as part of a reset operation state machine and prior to changing the processor information to its architecturally required post reset value. Such pre-reset processor information includes, for example one or more pre-reset values of the processor program counter (PC) and one or more pre-reset values of an operating-state mode register, both of which may be captured in one or more pre-reset capture storage devices which are then made available for evaluation purposes. Such pre-reset capture storage devices store pre-reset information in response to the reset and maintain the stored pre-reset information until another reset occurs.
摘要翻译： 处理器复位控制电路被配置为自动捕获存储在一个或多个硬件寄存器中的处理器信息的预复位值，作为复位操作状态机的一部分，并且在将处理器信息改变为其架构上所需的后置复位值之前。 这种预复位处理器信息包括例如处理器程序计数器（PC）的一个或多个预复位值和操作状态模式寄存器的一个或多个预复位值，它们都可以被捕获在一个或多个 更多的预复位捕获存储设备，然后可用于评估目的。 这种预复位捕获存储设备响应于重置来存储预复位信息，并保持所存储的预复位信息直到发生另一个复位。
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2.发明申请Methods and Apparatus for Saving Conditions Prior to a Reset for Post Reset Evaluation 有权在重置后复位评估之前保存条件的方法和装置公开(公告)号：US20130145137A1
公开(公告)日：2013-06-06
申请号：US13309623
申请日：2011-12-02
IPC分类号： G06F15/177 , G06F12/16
CPC分类号： G06F11/1441
摘要： A processor reset control circuit is configured to automatically capture a pre-reset value of processor information stored in one or more hardware registers, as part of a reset operation state machine and prior to changing the processor information to its architecturally required post reset value. Such pre-reset processor information includes, for example one or more pre-reset values of the processor program counter (PC) and one or more pre-reset values of an operating-state mode register, both of which may be captured in one or more pre-reset capture storage devices which are then made available for evaluation purposes. Such pre-reset capture storage devices store pre-reset information in response to the reset and maintain the stored pre-reset information until another reset occurs.
摘要翻译： 处理器复位控制电路被配置为自动捕获存储在一个或多个硬件寄存器中的处理器信息的预复位值，作为复位操作状态机的一部分，并且在将处理器信息改变为其架构上所需的后置复位值之前。 这种预复位处理器信息包括例如处理器程序计数器（PC）的一个或多个预复位值和操作状态模式寄存器的一个或多个预复位值，它们都可以被捕获在一个或多个 更多的预复位捕获存储设备，然后可用于评估目的。 这种预复位捕获存储设备响应于重置来存储预复位信息，并保持所存储的预复位信息直到发生另一个复位。
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公开(公告)号：US09092358B2
公开(公告)日：2015-07-28
申请号：US13371506
申请日：2012-02-13
CPC分类号： G06F12/1027 , G06F2212/6026 , G06F2212/6028 , G06F2212/654
摘要： Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.
摘要翻译： 用于内存管理单元（MMU）的系统和方法被配置为自动预先填充具有将要使用的地址转换条目的翻译后备缓冲器（TLB），从而减少TLB未命中率并提高性能。 可以预先填充TLB，其中可以基于预测来选择与预填充相对应的地址。 预测可以从外部设备导出，或者基于步幅值，其中步幅值可以是预定常数或基于访问模式动态地改变。 预填充TLB可以有效地消除从关键路径确定TLB未命中的地址转换所涉及的延迟。
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公开(公告)号：US09026744B2
公开(公告)日：2015-05-05
申请号：US11253307
申请日：2005-10-19
申请人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
发明人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
CPC分类号： G06F13/1621
摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.
摘要翻译： 本公开涉及一种用于在弱有序处理系统中强制执行强有序存储器访问请求的弱有序处理系统和方法。 处理系统包括多个存储器件和多个处理器。 每个处理器被配置为生成对一个或多个存储器设备的存储器访问请求，其中每个存储器访问请求具有可以被断言以指示强有序请求的属性。 处理系统还包括被配置为将处理器与存储器设备接口的总线互连，总线互连还被配置为基于属性来强制对存储器访问请求的排序限制。
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公开(公告)号：US08938602B2
公开(公告)日：2015-01-20
申请号：US13565434
申请日：2012-08-02
CPC分类号： G06F12/1009 , G06F12/145 , G06F2212/656 , Y02D10/13
摘要： A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The common page table can store virtual memory addresses to physical memory addresses mapping for memory chunks accessed by a job of an application. A page entry, within the common page table, can include a first set of attribute bits that defines accessibility of the memory chunk by the first processing unit, a second set of attribute bits that defines accessibility of the same memory chunk by the second processing unit, and physical address bits that define a physical address of the memory chunk.
摘要翻译： 第一处理单元和第二处理单元可以访问存储第一处理单元和第二处理单元共用的公共页表的系统存储器。 公共页表可以将虚拟内存地址存储到由应用程序的作业访问的存储块的物理内存地址映射。 公共页表内的页条目可以包括第一组属性位，其定义第一处理单元对存储块的可访问性;第二组属性位，其定义第二处理单元的相同存储块的可访问性 ，以及定义存储块的物理地址的物理地址位。
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6.发明授权公开(公告)号：US08924685B2
公开(公告)日：2014-12-30
申请号：US12777324
申请日：2010-05-11
CPC分类号： G06F9/34 , G06F9/35 , G06F12/1027 , G06F12/1081 , Y02D10/13
摘要： Configuring a surrogate memory accessing agent using an instruction for translating and storing a data value is described. In one embodiment, the instruction is received that includes a first operand specifying a data value to be translated and a second operand specifying a virtual address associated with a location of a surrogate memory accessing agent register in which to store the data value. The data value can be translated to a first physical address. The virtual address can be translated to a second physical address. The first physical address is stored in the surrogate memory accessing agent register based on the second physical address.
摘要翻译： 描述使用用于翻译和存储数据值的指令来配置代理存储器访问代理。 在一个实施例中，接收包括指定要转换的数据值的第一操作数和指定与其中存储数据值的代理存储器访问代理寄存器的位置相关联的虚拟地址的第二操作数的指令。 数据值可以转换为第一个物理地址。 虚拟地址可以转换为第二个物理地址。 第一物理地址基于第二物理地址存储在代理存储器访问代理寄存器中。
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公开(公告)号：US20140040593A1
公开(公告)日：2014-02-06
申请号：US13565434
申请日：2012-08-02
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/145 , G06F2212/656 , Y02D10/13
摘要： A first processing unit and a second processing unit can access a system memory that stores a common page table that is common to the first processing unit and the second processing unit. The common page table can store virtual memory addresses to physical memory addresses mapping for memory chunks accessed by a job of an application. A page entry, within the common page table, can include a first set of attribute bits that defines accessibility of the memory chunk by the first processing unit, a second set of attribute bits that defines accessibility of the same memory chunk by the second processing unit, and physical address bits that define a physical address of the memory chunk.
摘要翻译： 第一处理单元和第二处理单元可以访问存储第一处理单元和第二处理单元共用的公共页表的系统存储器。 公共页表可以将虚拟内存地址存储到由应用程序的作业访问的存储块的物理内存地址映射。 公共页表内的页条目可以包括第一组属性位，其定义第一处理单元对存储块的可访问性;第二组属性位，其定义第二处理单元的相同存储块的可访问性 ，以及定义存储块的物理地址的物理地址位。
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公开(公告)号：US20120226888A1
公开(公告)日：2012-09-06
申请号：US13371506
申请日：2012-02-13
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/6026 , G06F2212/6028 , G06F2212/654
摘要： Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) with address translation entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices, or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns. Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.
摘要翻译： 用于内存管理单元（MMU）的系统和方法被配置为自动预先填充具有将要使用的地址转换条目的翻译后备缓冲器（TLB），从而减少TLB未命中率并提高性能。 可以预先填充TLB，其中可以基于预测来选择与预填充相对应的地址。 预测可以从外部设备导出，或者基于步幅值，其中步幅值可以是预定常数，或者基于访问模式动态地改变。 预填充TLB可以有效地消除从关键路径确定TLB未命中的地址转换所涉及的延迟。
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公开(公告)号：US08239657B2
公开(公告)日：2012-08-07
申请号：US11672066
申请日：2007-02-07
申请人： Brian Joseph Kopec , Victor Roberts Augsburg , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Brian Joseph Kopec , Victor Roberts Augsburg , James Norris Dieffenderfer , Thomas Andrew Sartorius
IPC分类号： G06F12/04
CPC分类号： G06F12/04 , G06F12/1027 , G06F2212/655 , Y02D10/13
摘要： Address translation performance within a processor is improved by identifying an address that causes a boundary crossing between different pages in memory and linking address translation information associated with both memory pages. According to one embodiment of a processor, the processor comprises circuitry configured to recognize an access to a memory region crossing a page boundary between first and second memory pages. The circuitry is also configured to link address translation information associated with the first and second memory pages. Thus, responsive to a subsequent access the same memory region, the address translation information associated with the first and second memory pages is retrievable based on a single address translation.
摘要翻译： 通过识别导致存储器中的不同页面之间的边界交叉的地址以及链接与两个存储器页面相关联的地址转换信息来改进处理器内的地址转换性能。 根据处理器的一个实施例，处理器包括被配置为识别对跨越第一和第二存储器页之间的页边界的存储区的访问的电路。 电路还被配置为链接与第一和第二存储器页相关联的地址转换信息。 因此，响应于后续访问相同的存储器区域，可以基于单个地址转换来检索与第一和第二存储器页面相关联的地址转换信息。
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10.发明授权公开(公告)号：US08078803B2
公开(公告)日：2011-12-13
申请号：US11669245
申请日：2007-01-31
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804 , G06F12/128 , G06F2212/1028 , Y02D10/13
摘要： Techniques and methods are used to control allocations to a higher level cache of cache lines displaced from a lower level cache. The allocations of the displaced cache lines are prevented for displaced cache lines that are determined to be redundant in the next level cache, whereby castouts are controlled. To such ends, a line is selected to be displaced in a lower level cache. Information associated with the selected line is identified which indicates that the selected line is present in a higher level cache. An allocation of the selected line in the higher level cache is prevented based on the identified information.
摘要翻译： 技术和方法用于控制从较低级别缓存中移位的高速缓存行的更高级缓存的分配。 对于被确定为在下一级高速缓存中是冗余的移位高速缓存线，防止移位的高速缓存行的分配，从而控制转储。 为此，选择在下一级缓存中移位的行。 识别与所选行相关联的信息，其指示所选择的行存在于较高级别的高速缓存中。 基于所识别的信息来防止在较高级别高速缓存中的所选行的分配。
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