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    GPS receiver having RF front end power management and simultaneous baseband searching of frequency and code chip offset
    1.
    发明授权
    GPS receiver having RF front end power management and simultaneous baseband searching of frequency and code chip offset 失效
    GPS接收机具有RF前端功率管理和频率和码片偏移的同时基带搜索

    公开(公告)号：US07313421B2

    公开(公告)日：2007-12-25

    申请号：US10952967

    申请日：2004-09-28

    申请人： Thomas Dejanovic ,  Andrew Adams ,  Peter S. Single

    发明人： Thomas Dejanovic ,  Andrew Adams ,  Peter S. Single

    IPC分类号： H04B1/38

    CPC分类号： H04B1/1607 ,  G01S19/24 ,  G01S19/34

    摘要： A GPS receiver includes baseband resources for simultaneous determination of carrier frequency shift and code chip offset. Reduction in the power consumption of a receiver is achieved by managing the sampling rate of an analog-to-digital converter, the intermediate frequency of the RF front end, and the front end bandwidth so these are appropriate to the current function of the receiver. In a GPS receiver during signal tracking, the IF, front end bandwidth, and ADC sampling rate are set as high as possible; during signal acquisition, the IF and front end bandwidth are set to relatively low values, and the ADC sample rate is set to a high value; and during ephemeris download, the IF, front end bandwidth, and the ADC sample rate are set to relatively low values. When a low battery condition is detected, the IF, front end bandwidth, and the ADC sample rate are set to relatively low values regardless of whether the GPS receiver is in the signal acquisition mode, signal tracking mode, or ephemeris download mode.

    摘要翻译： GPS接收机包括用于同时确定载波频移和码片偏移的基带资源。 通过管理模拟 - 数字转换器的采样率，RF前端的中频和前端带宽来实现接收机功耗的降低，从而适合接收机的当前功能。 在信号跟踪期间的GPS接收机中，IF，前端带宽和ADC采样率设置得尽可能高; 在信号采集期间，IF和前端带宽设置为相对较低的值，ADC采样率设置为高值; 并且在星历下载期间，IF，前端带宽和ADC采样率被设置为相对较低的值。 当检测到低电量条件时，无论GPS接收机是处于信号采集模式，信号跟踪模式还是星历下载模式，IF，前端带宽和ADC采样率均被设置为相对较低的值。

    Coarse and fine location for tagged items
    3.
    发明申请
    Coarse and fine location for tagged items 审中-公开
    标记物品的粗细位置

    公开(公告)号：US20080157970A1

    公开(公告)日：2008-07-03

    申请号：US11725046

    申请日：2007-03-16

    申请人： Peter S. Single ,  Geoffrey J. Smith

    发明人： Peter S. Single ,  Geoffrey J. Smith

    IPC分类号： G08B13/14 ,  G08B1/08

    CPC分类号： G01S13/878 ,  G01S5/0263 ,  G08B21/0244 ,  G08B21/0275

    摘要： The location of an item may be determined by first determining a coarse location and then a fine location. In one example, a coarse position of a tagged item is determined using a coarse positioning system and the item's tag. A mobile unit, carrying a fine positioning system, is moved to the determined coarse position. Then, a fine position of the tagged item is determined by communicating between the fine positioning system of the moved mobile unit and the item's tag.

    摘要翻译： 项目的位置可以通过首先确定粗略位置，然后确定精细位置来确定。 在一个示例中，使用粗定位系统和项目的标签来确定标记项目的粗略位置。 携带精细定位系统的移动单元被移动到确定的粗略位置。 然后，通过移动的移动单元的精细定位系统和项目的标签之间的通信来确定标记的项目的精细位置。

    Sine wave synthesizer
    4.
    发明授权
    Sine wave synthesizer 失效
    正弦波合成器

    公开(公告)号：US4631694A

    公开(公告)日：1986-12-23

    申请号：US604718

    申请日：1984-04-27

    申请人： Peter S. Single

    发明人： Peter S. Single

    IPC分类号： G06J1/00 ,  H03C3/00 ,  H04L27/12 ,  G06F1/02

    CPC分类号： H04L27/122 ,  G06J1/00 ,  H03C3/00

    摘要： A sine wave synthesizer is employed in an analog signal processing integrated circuit. The circuit includes an integrator driven from a plurality of integration constant capacitors which are sequentially selected by a clocked decoder. Each capacitor is selected by coupling it between the integrator and a switched reference source. The capacitors are selected so that their sequential selection produces a sine wave approximating current in four increments. A first increment of a sine wave is produced according to an ascending selection of integration constant capacitors. Thereafter, the capacitors are selected in reverse in a descending manner to produce a second increment of the sine wave. The switched capacitor phasing circuit is then operated to invert the sine wave signal to produce the third and fourth increments having a negative instead of a positive excursion. The frequency of the sine wave is controlled by the decoder clock input. An output filter stage converts the digitally produced sine wave increments into a smooth sine wave output. This filter is provided with selectable time constants to allow operation at different selected frequencies.

    摘要翻译： 在模拟信号处理集成电路中采用正弦波合成器。 该电路包括由多个积分常数电容器驱动的积分器，其由时钟解码器依次选择。 通过在积分器和开关参考源之间耦合来选择每个电容器。 选择电容器使得其顺序选择以四个增量产生近似电流的正弦波。 根据积分常数电容器的上升选择产生正弦波的第一增量。 此后，以降序的方式相反地选择电容器，以产生正弦波的第二增量。 然后操作开关电容器定相电路以反转正弦波信号以产生具有负的而不是正偏移的第三和第四增量。 正弦波的频率由解码器时钟输入控制。 输出滤波器级将数字产生的正弦波增量转换为平滑正弦波输出。 该滤波器具有可选择的时间常数，以允许在不同的选定频率下工作。

    Low offset CMOS comparator circuit
    5.
    发明授权
    Low offset CMOS comparator circuit 失效
    低偏移CMOS比较器电路

    公开(公告)号：US4602168A

    公开(公告)日：1986-07-22

    申请号：US594070

    申请日：1984-03-28

    申请人： Peter S. Single

    发明人： Peter S. Single

    IPC分类号： H03K5/24

    CPC分类号： H03K5/2445

    摘要： A CMOS comparator circuit is disclosed in which a low offset is achieved without trimming. The input stage is composed of a pair of bipolar transistors which have lateral non-dedicated collectors that operate in parallel with the substrate dedicated collectors. The input stage includes matched load devices and is followed by an amplifier having a differential to single ended converter.

    摘要翻译： 公开了一种CMOS比较器电路，其中在不修整的情况下实现低偏移。 输入级由一对双极晶体管组成，双极晶体管具有与衬底专用集电极并联工作的侧面非专用集电极。 输入级包括匹配的负载器件，之后是具有差分至单端转换器的放大器。

    Digital FSK demodulator circuit
    6.
    发明授权
    Digital FSK demodulator circuit 失效
    数字FSK解调电路

    公开(公告)号：US4568882A

    公开(公告)日：1986-02-04

    申请号：US655780

    申请日：1984-10-01

    申请人： Peter S. Single

    发明人： Peter S. Single

    IPC分类号： H04L27/152 ,  H03K9/06 ,  H03D3/00 ,  H03D3/06

    CPC分类号： H04L27/1525

    摘要： An FSK demodulator is disclosed suitable for use in a CMOS IC using switched capacitor circuits. The mark and space filters are each modified to produce sine and cosine outputs. These outputs are rectified separately and the result summed. The summed outputs are passed through low pass filters and applied to a comparator which determines which of the mark and space signals is dominant. The invention substantially reduces the size of the demodulator filter capacitors and improves the demodulation signal to noise ratio.

    摘要翻译： 公开了适用于使用开关电容器电路的CMOS IC的FSK解调器。 标记和空间滤波器都被修改为产生正弦和余弦输出。 这些输出单独纠正，结果相加。 相加的输出通过低通滤波器并且被施加到比较器，该比较器确定哪个标记和空间信号占主导地位。 本发明基本上减小了解调滤波电容器的尺寸，提高了解调信噪比。

    Low power range and position determination for wireless communication nodes
    10.
    发明申请
    Low power range and position determination for wireless communication nodes 审中-公开
    低功率范围和无线通信节点的位置确定

    公开(公告)号：US20090054096A1

    公开(公告)日：2009-02-26

    申请号：US11894462

    申请日：2007-08-20

    申请人： Peter S. Single

    发明人： Peter S. Single

    IPC分类号： H04Q7/20

    CPC分类号： H04W52/325 ,  H04B17/24 ,  H04B17/318 ,  H04B17/382 ,  H04W8/005

    摘要： Range to a wireless communications node and position relative to one or more wireless communication nodes can be determined with a reduced amount of power consumption. In one example, a probe request is sent at a first power level. Probe responses in response to the probe request are listened for. The number of different radios from which a probe response has been received is counted and compared to a threshold. If the count does not exceed the threshold, then a second different probe request is sent.

    摘要翻译： 可以以减少的功耗量确定无线通信节点和相对于一个或多个无线通信节点的位置的范围。 在一个示例中，以第一功率电平发送探测请求。 响应探测请求的探测响应将被收听。 计数接收到探头响应的不同无线电的数量，并与阈值进行比较。 如果计数不超过阈值，则发送第二个不同的探测请求。