公开(公告)号：US5093908A

公开(公告)日：1992-03-03

申请号：US339285

申请日：1989-04-17

申请人： Thomas J. Beacom ,  Jeffrey D. Brown ,  Mark R. Funk ,  Scott A. Hilker ,  Daniel G. Young

发明人： Thomas J. Beacom ,  Jeffrey D. Brown ,  Mark R. Funk ,  Scott A. Hilker ,  Daniel G. Young

IPC分类号： G06F9/38

CPC分类号： G06F9/3877

摘要： A tightly-coupled main processor and coprocessor overlap the execution of sequential instructions when apparent sequential operation and precise exception interrupts can be assured. Logic detects all conditions under which these criteria might potentially be violated in the coprocessor before it has finished performing an instruction, and holds off the main processor from executing a subsequent instruction.

公开(公告)号：US4996660A

公开(公告)日：1991-02-26

申请号：US339268

申请日：1989-04-17

申请人： Thomas J. Beacom ,  Donald L. Freerksen

发明人： Thomas J. Beacom ,  Donald L. Freerksen

IPC分类号： G06F7/483 ,  G06F7/52 ,  G06F7/535

CPC分类号： G06F7/535 ,  G06F2207/5352 ,  G06F7/4873 ,  G06F7/49947 ,  G06F7/49957

摘要： A multiple selector logic circuit for selecting divisor multiples in 2-bit, non-restoring divide sequences, which provides a proper and accurate quotient result and remainder, and which produces rounding and indication of exact or inexact result in conformance with ANSI/IEEE Standard 754-1985; the multiple selector logic circuit incorporates semiconductor circuits including a multiplier table having a particular matrix of multipliers which meet the standard.

公开(公告)号：US4170039A

公开(公告)日：1979-10-02

申请号：US925148

申请日：1978-07-17

申请人： Thomas J. Beacom ,  Douglas M. Kindseth ,  Glen R. Mitchell

发明人： Thomas J. Beacom ,  Douglas M. Kindseth ,  Glen R. Mitchell

IPC分类号： G06F12/10 ,  G06F9/10

CPC分类号： G06F12/1027

摘要： Address translation apparatus is provided where the address to be translated is compared with two address translation candidates sequentially. The virtual address to be translated is contained in a virtual address register. A field of bits within the virtual address are presented simultaneously as an address to a translation table and a pre-translation table where the pre-translation table has two entries per row and each entry contains some of the virtual address bits of corresponding candidates in the translation table. The pre-translation table is quite narrow compared to the translation table and is preferably, but not necessarily, implemented in latches or as a very fast array compared to the translation table. The selected entries from the pre-translation table are compared with corresponding bits from the virtual address register and the results of the precompare generate an address bit which together with the other address bits select the candidate from the translation table which is more likely to compare with a larger group of address bits from the virtual address register. In the event both entries from the pre-translation table compare with the corresponding bits from the virtual address register and the selected candidate from the translation table does not compare with the larger group of address bits from the virtual address register, the address bit from the precompare is forced to an opposite state whereby the other candidate is selected.