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1.发明授权Method and apparatus for executing instructions in a single sequential instruction stream in a main processor and a coprocessor 失效在主处理器和共处理器中的单个指令流中执行指令的方法和装置
公开(公告)号：US5093908A
公开(公告)日：1992-03-03
申请号：US339285
申请日：1989-04-17
IPC分类号： G06F9/38
CPC分类号： G06F9/3877
摘要： A tightly-coupled main processor and coprocessor overlap the execution of sequential instructions when apparent sequential operation and precise exception interrupts can be assured. Logic detects all conditions under which these criteria might potentially be violated in the coprocessor before it has finished performing an instruction, and holds off the main processor from executing a subsequent instruction.
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公开(公告)号：US4941120A
公开(公告)日：1990-07-10
申请号：US339347
申请日：1989-04-17
CPC分类号： G06F7/483 , G06F7/49936 , G06F7/49947
摘要： Apparatus for enhancing certain floating point arithmetic operations, by examining the initial operands and the exponent and fractional results and predicting when the steps of postnormalization and rounding can be skipped. The fraction result format enables a prediction of normalization and rounding under each of the addition, subtraction and multiplication possibilities, and under each of the various choices of rounding mode which are used in floating point arithmetic.
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3.发明授权
公开(公告)号：US4926370A
公开(公告)日：1990-05-15
申请号：US339348
申请日：1989-04-17
CPC分类号： G06F7/483 , G06F7/49936 , G06F7/49957
摘要： A method and apparatus for processing postnormalization and rounding in parallel in floating point arithmetic circuits. The fractional result of a floating point arithmetic operation is simultaneously passed to a normalized circuit and a round circuit, and the first two bit positions of the fractional result are examined. If the 2-bit format is 1.X the round circuit is activated; if the 2-bit format is 0.1X the fractional result is shifted left one position and the round circuit is activated; if the 2-bit format is in neither of the above formats the normalize circuit is activated. In no event is it necessary to activate sequentially the normalize circuit and the round circuit.
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公开(公告)号：USH1222H
公开(公告)日：1993-08-03
申请号：US814934
申请日：1991-12-30
申请人： Jeffrey D. Brown , Roy R. Faget , Scott A. Hilker
发明人： Jeffrey D. Brown , Roy R. Faget , Scott A. Hilker
CPC分类号： G06F7/483 , G06F7/49952
摘要： An apparatus for determining the correct value to be assigned to the "sticky-bit" (S) position as a consequence of an arithmetic floating point multiply, divide or square root operation. The apparatus measures the number of trailing zeroes in the operand registers, performs a sum or difference calculation of these values, and compares the result with a third value to determine the sticky-bit value.
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公开(公告)号：US20130346463A1
公开(公告)日：2013-12-26
申请号：US13529619
申请日：2012-06-21
申请人： Scott A. Hilker , George Q. Phan
发明人： Scott A. Hilker , George Q. Phan
IPC分类号： G06F7/52
CPC分类号： G06F7/52 , G06F7/483 , G06F7/4876 , G06F7/5318 , G06F7/5338 , G06F7/5443 , G06F2207/382 , G06F2207/3884
摘要： The disclosed embodiments relate to apparatus for accurately, efficiently and quickly executing a multiplication instruction. The disclosed embodiments can provide a multiplier module having an optimized layout that can help speed up computation of a result during a multiply operation so that cycle delay can be reduced and so that power consumption can be reduced.
摘要翻译： 所公开的实施例涉及用于准确，有效和快速地执行乘法指令的装置。 所公开的实施例可以提供具有优化布局的乘法器模块，其可以在乘法运算期间有助于加速结果的计算，从而可以减少周期延迟，从而可以降低功耗。
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6.发明授权Arithmetic processing unit that performs multiply and multiply-add operations with saturation and method therefor 有权使用饱和度进行乘法和乘法运算的算术处理单元及其方法公开(公告)号：US08316071B2
公开(公告)日：2012-11-20
申请号：US12472715
申请日：2009-05-27
申请人： Kevin A. Hurd , Scott A. Hilker
发明人： Kevin A. Hurd , Scott A. Hilker
CPC分类号： G06F7/4991 , G06F7/49921 , G06F7/53 , G06F7/5443
摘要： Sum and carry signals are formed representing a product of a first and a second operand. A bias signal is formed having a value determined by a sign of a product of the first and the second operand. An output signal is provided based on an addition of the sum signal, the carry signal, a sign-extended addend, and the bias signal. A portion of the output signal, a saturated minimum value, or a saturated maximum value, is selected as a final result based on the sign of the product and a sign of the output signal.
摘要翻译： 形成表示第一和第二操作数的乘积的和和进位信号。 形成具有由第一和第二操作数的乘积的符号确定的值的偏置信号。 基于和信号，进位信号，符号扩展加数和偏置信号的相加来提供输出信号。 基于产品的符号和输出信号的符号，选择输出信号的一部分，饱和最小值或饱和最大值作为最终结果。
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公开(公告)号：US20110208951A1
公开(公告)日：2011-08-25
申请号：US12709945
申请日：2010-02-22
申请人： Scott A. Hilker
发明人： Scott A. Hilker
CPC分类号： G06F9/30036 , G06F9/30109
摘要： A method of executing a program instruction is disclosed. An instruction operand stored at a register of a register file is accessed by an execution unit using multiple access requests. A first portion of the execution unit provides a first access request to a first access port of the register file to access a first portion of the instruction operand. A second portion of the execution unit provides a second access request to a second access port of the register file to access a second portion of the instruction operand. The register file can be configured into physically separate portions.
摘要翻译： 公开了执行程序指令的方法。 存储在寄存器文件的寄存器中的指令操作数由执行单元使用多个访问请求来访问。 执行单元的第一部分向寄存器文件的第一访问端口提供第一访问请求以访问指令操作数的第一部分。 执行单元的第二部分向寄存器文件的第二访问端口提供第二访问请求以访问指令操作数的第二部分。 寄存器文件可以配置成物理上分开的部分。
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公开(公告)号：US08996601B2
公开(公告)日：2015-03-31
申请号：US13529619
申请日：2012-06-21
申请人： Scott A. Hilker , George Q. Phan
发明人： Scott A. Hilker , George Q. Phan
CPC分类号： G06F7/52 , G06F7/483 , G06F7/4876 , G06F7/5318 , G06F7/5338 , G06F7/5443 , G06F2207/382 , G06F2207/3884
摘要： The disclosed embodiments relate to apparatus for accurately, efficiently and quickly executing a multiplication instruction. The disclosed embodiments can provide a multiplier module having an optimized layout that can help speed up computation of a result during a multiply operation so that cycle delay can be reduced and so that power consumption can be reduced.
摘要翻译： 所公开的实施例涉及用于准确，有效和快速地执行乘法指令的装置。 所公开的实施例可以提供具有优化布局的乘法器模块，其可以在乘法运算期间有助于加速结果的计算，从而可以减少周期延迟，从而可以降低功耗。
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公开(公告)号：US20140136587A1
公开(公告)日：2014-05-15
申请号：US13674220
申请日：2012-11-12
IPC分类号： G06F7/68
CPC分类号： G06F7/483 , G06F7/49936 , G06F7/5443
摘要： The present application provides a method and apparatus for supporting denormal numbers in a floating point multiply-add unit (FMAC). One embodiment of the FMAC is configurable to add a product of first and second operands to a third operand. This embodiment of the FMAC is configurable to determine a minimum exponent shift for a sum of the product and the third operand by subtracting a minimum normal exponent from a product exponent of the product. This embodiment of the FMAC is also configurable to cause bits representing the sum to be left shifted by the minimum exponent shift if a third exponent of the third operand is less than or equal to the product exponent and the minimum exponent shift is less than or equal to a predicted left shift for the sum.
摘要翻译： 本申请提供了一种用于支持浮点乘法单元（FMAC）中的反常数的方法和装置。 FMAC的一个实施例可配置为将第一和第二操作数的乘积添加到第三操作数。 FMAC的该实施例可配置为通过从乘积的乘积指数减去最小正态指数来确定乘积和第三操作数之和的最小指数偏移。 如果FMAC的这个实施例如果第三操作数的第三指数小于或等于乘积指数并且最小指数移位小于或等于，则可配置为使表示和的位移动移位最小指数移位 到总和的预测左移。
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10.发明申请ARITHMETIC PROCESSING UNIT THAT PERFORMS MULTIPLY AND MULTIPLY-ADD OPERATIONS WITH SATURATION AND METHOD THEREFOR 有权具有饱和度的多项式和多项式运算的算术处理单元及其方法公开(公告)号：US20100306301A1
公开(公告)日：2010-12-02
申请号：US12472715
申请日：2009-05-27
申请人： Kevin A. Hurd , Scott A. Hilker
发明人： Kevin A. Hurd , Scott A. Hilker
IPC分类号： G06F7/38
CPC分类号： G06F7/4991 , G06F7/49921 , G06F7/53 , G06F7/5443
摘要： Sum and carry signals are formed representing a product of a first and a second operand. A bias signal is formed having a value determined by a sign of a product of the first and the second operand. An output signal is provided based on an addition of the sum signal, the carry signal, a sign-extended addend, and the bias signal. A portion of the output signal, a saturated minimum value, or a saturated maximum value, is selected as a final result based on the sign of the product and a sign of the output signal.
摘要翻译： 形成表示第一和第二操作数的乘积的和和进位信号。 形成具有由第一和第二操作数的乘积的符号确定的值的偏置信号。 基于和信号，进位信号，符号扩展加数和偏置信号的相加来提供输出信号。 基于产品的符号和输出信号的符号，选择输出信号的一部分，饱和最小值或饱和最大值作为最终结果。
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