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公开(公告)号:US20090162988A1
公开(公告)日:2009-06-25
申请号:US12395076
申请日:2009-02-27
申请人: Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, JR. , George Chang
发明人: Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, JR. , George Chang
IPC分类号: H01L21/77 , H01L21/762
CPC分类号: H01L29/8613 , H01L27/0255 , H01L29/8618 , Y10S257/929 , Y10S438/966 , Y10S438/983
摘要: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.
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2.
公开(公告)号:US20090079022A1
公开(公告)日:2009-03-26
申请号:US11859570
申请日:2007-09-21
申请人: Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, JR. , George Chang
发明人: Thomas Keena , Ki Chang , Francine Y. Robb , Mingjiao Liu , Ali Salih , John Michael Parsey, JR. , George Chang
IPC分类号: H01L29/866 , H01L21/329
CPC分类号: H01L29/8613 , H01L27/0255 , H01L29/8618 , Y10S257/929 , Y10S438/966 , Y10S438/983
摘要: In one embodiment, the ESD device uses highly doped P and N regions deep within the ESD device to form a zener diode that has a controlled breakdown voltage.
摘要翻译: 在一个实施例中,ESD器件使用ESD器件内深度的高掺杂P和N区域形成具有受控击穿电压的齐纳二极管。
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公开(公告)号:US20090079001A1
公开(公告)日:2009-03-26
申请号:US11859624
申请日:2007-09-21
申请人: Ali Salih , Mingjiao Liu , Sudhama C. Shastri , Thomas Keena , Gordon M. Grivna , John Michael Parsey, JR. , Francine Y. Robb , Ki Chang
发明人: Ali Salih , Mingjiao Liu , Sudhama C. Shastri , Thomas Keena , Gordon M. Grivna , John Michael Parsey, JR. , Francine Y. Robb , Ki Chang
CPC分类号: H01L27/0255 , H01L23/60 , H01L2924/0002 , Y10S438/983 , H01L2924/00
摘要: In one embodiment, an ESD device is configured to include a zener diode and a P-N diode.
摘要翻译: 在一个实施例中,ESD器件被配置为包括齐纳二极管和P-N二极管。
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公开(公告)号:US20110021009A1
公开(公告)日:2011-01-27
申请号:US12890878
申请日:2010-09-27
IPC分类号: H01L21/22
CPC分类号: H01L27/0255 , H01L29/8611 , H01L29/866
摘要: In one embodiment, an ESD device is configured to include a zener diode and a P-N diode and to have a conductor that provides a current path between the zener diode and the P-N diode.
摘要翻译: 在一个实施例中,ESD器件被配置为包括齐纳二极管和P-N二极管,并且具有在齐纳二极管和P-N二极管之间提供电流路径的导体。
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公开(公告)号:US20100006889A1
公开(公告)日:2010-01-14
申请号:US12170630
申请日:2008-07-10
IPC分类号: H01L29/866 , H01L21/20
CPC分类号: H01L27/0255 , H01L29/8611 , H01L29/866
摘要: In one embodiment, an ESD device is configured to include a zener diode and a P-N diode and to have a conductor that provides a current path between the zener diode and the P-N diode.
摘要翻译: 在一个实施例中,ESD器件被配置为包括齐纳二极管和P-N二极管,并且具有在齐纳二极管和P-N二极管之间提供电流路径的导体。
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公开(公告)号:US20120049320A1
公开(公告)日:2012-03-01
申请号:US12871390
申请日:2010-08-30
IPC分类号: H01L21/82 , H01L21/768
CPC分类号: H01L23/481 , H01L21/76898 , H01L27/0207 , H01L28/10 , H01L28/20 , H01L28/91 , H01L29/6609 , H01L29/66106 , H01L29/861 , H01L29/866 , H01L29/945 , H01L2224/0401 , H01L2224/05 , H01L2224/05025 , H01L2924/1301 , H01L2924/1305 , H01L2924/00
摘要: A semiconductor substrate can be patterned to define a trench and a feature. In an embodiment, the trench can be formed such that after filling the trench with a material, a bottom portion of the filled trench may be exposed during a substrate thinning operation. In another embodiment, the trench can be filled with a thermal oxide. The feature can have a shape that reduces the likelihood that a distance between the feature and a wall of the trench will be changed during subsequent processing. A structure can be at least partly formed within the trench, wherein the structure can have a relatively large area by taking advantage of the depth of the trench. The structure can be useful for making electronic components, such as passive components and through-substrate vias. The process sequence to define the trenches and form the structures can be tailored for many different process flows.
摘要翻译: 半导体衬底可以被图案化以限定沟槽和特征。 在一个实施例中,可以形成沟槽,使得在用材料填充沟槽之后,填充沟槽的底部部分可以在衬底变薄操作期间暴露。 在另一个实施例中,沟槽可以用热氧化物填充。 该特征可以具有减小在后续处理期间在特征和沟槽的壁之间的距离将被改变的可能性的形状。 结构可以至少部分地形成在沟槽内,其中通过利用沟槽的深度,该结构可以具有相对大的面积。 该结构可用于制造电子部件,例如无源部件和贯穿基板通孔。 定义沟槽和形成结构的过程顺序可以针对许多不同的工艺流程进行定制。
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公开(公告)号:US20130277807A1
公开(公告)日:2013-10-24
申请号:US13920675
申请日:2013-06-18
IPC分类号: H01L23/48
CPC分类号: H01L23/481 , H01L21/76898 , H01L27/0207 , H01L28/10 , H01L28/20 , H01L28/91 , H01L29/6609 , H01L29/66106 , H01L29/861 , H01L29/866 , H01L29/945 , H01L2224/0401 , H01L2224/05 , H01L2224/05025 , H01L2924/1301 , H01L2924/1305 , H01L2924/00
摘要: A semiconductor substrate can be patterned to define a trench and a feature. In an embodiment, the trench can be formed such that after filling the trench with a material, a bottom portion of the filled trench may be exposed during a substrate thinning operation. In another embodiment, the trench can be filled with a thermal oxide. The feature can have a shape that reduces the likelihood that a distance between the feature and a wall of the trench will be changed during subsequent processing. A structure can be at least partly formed within the trench, wherein the structure can have a relatively large area by taking advantage of the depth of the trench. The structure can be useful for making electronic components, such as passive components and through-substrate vias. The process sequence to define the trenches and form the structures can be tailored for many different process flows.
摘要翻译: 半导体衬底可以被图案化以限定沟槽和特征。 在一个实施例中,可以形成沟槽,使得在用材料填充沟槽之后,填充沟槽的底部部分可以在衬底变薄操作期间暴露。 在另一个实施例中,沟槽可以用热氧化物填充。 该特征可以具有减小在后续处理期间在特征和沟槽的壁之间的距离将被改变的可能性的形状。 结构可以至少部分地形成在沟槽内,其中通过利用沟槽的深度,该结构可以具有相对大的面积。 该结构可用于制造电子部件,例如无源部件和贯穿基板通孔。 定义沟槽和形成结构的过程顺序可以针对许多不同的工艺流程进行定制。
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公开(公告)号:US20110233635A1
公开(公告)日:2011-09-29
申请号:US13005947
申请日:2011-01-13
CPC分类号: H01L29/7813 , H01L21/76232 , H01L29/0634 , H01L29/0649 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734
摘要: In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core.
摘要翻译: 在一个实施例中,形成具有沟槽结构的半导体器件。 沟槽结构包括沿着沟槽的暴露的上表面形成的单晶半导体插塞。 在一个实施例中,单晶半导体插塞密封沟槽以形成密封的芯。
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公开(公告)号:US20100059815A1
公开(公告)日:2010-03-11
申请号:US12206541
申请日:2008-09-08
IPC分类号: H01L29/78 , H01L27/06 , H01L21/336
CPC分类号: H01L29/7813 , H01L21/76232 , H01L29/0634 , H01L29/0649 , H01L29/0878 , H01L29/1095 , H01L29/41766 , H01L29/66727 , H01L29/66734
摘要: In one embodiment, a semiconductor device is formed having a trench structure. The trench structure includes a single crystalline semiconductor plug formed along exposed upper surfaces of the trench. In one embodiment, the single crystalline semiconductor plug seals the trench to form a sealed core.
摘要翻译: 在一个实施例中,形成具有沟槽结构的半导体器件。 沟槽结构包括沿着沟槽的暴露的上表面形成的单晶半导体插塞。 在一个实施例中,单晶半导体插塞密封沟槽以形成密封的芯。
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