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    Structure For An Integrated Circuit That Employs Multiple Interfaces
    2.
    发明申请
    Structure For An Integrated Circuit That Employs Multiple Interfaces 审中-公开
    采用多个接口的集成电路的结构

    公开(公告)号：US20090222251A1

    公开(公告)日：2009-09-03

    申请号：US12347989

    申请日：2008-12-31

    申请人： Tilman Gloekler ,  Ingemar Holm ,  Ralph C. Koester ,  Mack Wayne Riley ,  Shoji Sawamura ,  Iwao Takiguchi

    发明人： Tilman Gloekler ,  Ingemar Holm ,  Ralph C. Koester ,  Mack Wayne Riley ,  Shoji Sawamura ,  Iwao Takiguchi

    IPC分类号： G06F17/50

    CPC分类号： G01R31/318555 ,  G01R31/318558 ,  G01R31/318572 ,  G06F11/2236

    摘要： A design structure for a integrated circuit interfacing system may be embodied in a machine readable medium for designing, manufacturing or testing a integrated circuit. In one embodiment, the design structure specifies an integrated circuit that includes multiple interfaces. The design structure may specify that each of the interfaces couples to a respective set of registers or storage elements on the integrated circuit. The design structure may also specify a bridge circuit on the integrated circuit that switchably couples the two interfaces together such that one interface may communicate with the registers that associate with that interface as well as the registers that associate with the other interface.

    摘要翻译： 用于集成电路接口系统的设计结构可以体现在用于设计，制造或测试集成电路的机器可读介质中。 在一个实施例中，设计结构指定包括多个接口的集成电路。 设计结构可以指定每个接口耦合到集成电路上相应的一组寄存器或存储元件。 该设计结构还可以指定集成电路上的桥接电路，其可切换地将两个接口耦合在一起，使得一个接口可以与与该接口相关联的寄存器以及与另一接口相关联的寄存器通信。

    High speed on-chip serial link apparatus
    3.
    发明授权
    High speed on-chip serial link apparatus 有权
    高速片上串行连接装置

    公开(公告)号：US07711875B2

    公开(公告)日：2010-05-04

    申请号：US12013913

    申请日：2008-01-14

    申请人： Tilman Gloekler ,  Ingemar Holm ,  Ralph C. Koester ,  Mack W. Riley

    发明人： Tilman Gloekler ,  Ingemar Holm ,  Ralph C. Koester ,  Mack W. Riley

    IPC分类号： G06F13/12 ,  G06F13/00

    CPC分类号： G06F13/4054

    摘要： A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.

    摘要翻译： 提供了一种将外部低速工业标准接口转换为片上高速串行链路（HSSL）的转换器装置和方法。 本发明的转换器优选放置在外部接口附近。 HSSL以系统时钟速度运行，因此，HSSL接口信号可以像任何其他定时信号一样轻松处理，便于物理设计过程。 因为在外部接口附近的转换器中执行同步一次，并且沿着本发明的HSSL的信号可以像任何其他定时信号一样被处理，因此消除了对芯片的每个处理元件中的接口单元进行同步的需要。 因此，减少了本发明使用的复杂性和硅面积。 该转换器可实现串行接口的最大速度，这在上电复位，制造测试和芯片调试方面至关重要。

    High Speed On-Chip Serial Link Apparatus
    4.
    发明申请
    High Speed On-Chip Serial Link Apparatus 有权
    高速片上串行链路设备

    公开(公告)号：US20080133800A1

    公开(公告)日：2008-06-05

    申请号：US12013913

    申请日：2008-01-14

    申请人： Tilman Gloekler ,  Ingemar Holm ,  Ralph C. Koester ,  Mack W. Riley

    发明人： Tilman Gloekler ,  Ingemar Holm ,  Ralph C. Koester ,  Mack W. Riley

    IPC分类号： G06F1/12

    CPC分类号： G06F13/4054

    摘要： A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.

    摘要翻译： 提供了一种将外部低速工业标准接口转换为片上高速串行链路（HSSL）的转换器装置和方法。 本发明的转换器优选放置在外部接口附近。 HSSL以系统时钟速度运行，因此，HSSL接口信号可以像任何其他定时信号一样轻松处理，便于物理设计过程。 因为在外部接口附近的转换器中执行同步一次，并且沿着本发明的HSSL的信号可以像任何其他定时信号一样被处理，因此消除了对芯片的每个处理元件中的接口单元进行同步的需要。 因此，减少了本发明使用的复杂性和硅面积。 该转换器可实现串行接口的最大速度，这在上电复位，制造测试和芯片调试方面至关重要。

    High speed on-chip serial link apparatus and method
    5.
    发明授权
    High speed on-chip serial link apparatus and method 有权
    高速片上串行连接装置及方法

    公开(公告)号：US07430624B2

    公开(公告)日：2008-09-30

    申请号：US11242676

    申请日：2005-10-04

    申请人： Tilman Gloekler ,  Ingemar Holm ,  Ralph C. Koester ,  Mack W. Riley

    发明人： Tilman Gloekler ,  Ingemar Holm ,  Ralph C. Koester ,  Mack W. Riley

    IPC分类号： G06F13/12 ,  G06F13/00

    CPC分类号： G06F13/4054

    摘要： A converter apparatus and method are provided that transforms an external low speed industry standard interface into an on-chip high speed serial link (HSSL). The converter of the present invention is preferably placed in close vicinity of the external interface. The HSSL operates at the system clock speed and, as a result, the HSSL interface signals can be readily treated like any other timed signal facilitating the physical design process. Because synchronization is performed once in the converter near the external interface and the signals along the HSSL of the present invention may be treated like any other timed signal, the need for interface units in each processing element of the chip to perform synchronization is eliminated. Thus, the complexity and silicon area used by the present invention is reduced. The converter enables the maximum speed for the serial interface, which is crucial in power-on-reset, manufacturing testing, and chip debugging.

    摘要翻译： 提供了一种将外部低速工业标准接口转换为片上高速串行链路（HSSL）的转换器装置和方法。 本发明的转换器优选放置在外部接口附近。 HSSL以系统时钟速度运行，因此，HSSL接口信号可以像任何其他定时信号一样轻松处理，便于物理设计过程。 因为在外部接口附近的转换器中执行同步一次，并且沿着本发明的HSSL的信号可以像任何其他定时信号一样被处理，因此消除了对芯片的每个处理元件中的接口单元进行同步的需要。 因此，减少了本发明使用的复杂性和硅面积。 该转换器可实现串行接口的最大速度，这在上电复位，制造测试和芯片调试方面至关重要。

    System and method for distributing signal with efficiency over microprocessor
    7.
    发明授权
    System and method for distributing signal with efficiency over microprocessor 失效
    通过微处理器分配信号的系统和方法

    公开(公告)号：US08055809B2

    公开(公告)日：2011-11-08

    申请号：US12343594

    申请日：2008-12-24

    申请人： Matthias Fertig ,  Tilman Gloekler ,  Ralph C. Koester ,  Alexander Erik Mericas ,  Thomas Pflueger ,  Daniel Becker

    发明人： Matthias Fertig ,  Tilman Gloekler ,  Ralph C. Koester ,  Alexander Erik Mericas ,  Thomas Pflueger ,  Daniel Becker

    IPC分类号： G06F3/00

    CPC分类号： G06F13/4247 ,  G06F11/3466 ,  G06F11/348 ,  G06F11/349 ,  G06F2201/88

    摘要： A system and associated method for distributing signals with efficiency over a microprocessor. A performance monitoring unit (PMU) sends configuration signals to a unit to monitor an event occurring on the unit. The unit is attached to a configuration bus and an event bus that are daisy-chained from PMU to other units in the microprocessor. The configuration bus transmits configuration signals from the PMU to the unit to set the unit to report the event. The unit sends event signals to the PMU through the event bus. The unit is configured upon receiving configuration signals comprising a base address of a bus ramp of the unit. A number of units and a number of events for monitoring is flexibly selected by adjusting a length of bit fields within configuration signals.

    摘要翻译： 一种用于通过微处理器分配信号的系统和相关方法。 性能监视单元（PMU）将配置信号发送到单元以监视本机发生的事件。 该单元连接到配置总线和从PMU菊花链到微处理器中的其他单元的事件总线。 配置总线将配置信号从PMU发送到单元以设置单元以报告事件。 该单元通过事件总线向PMU发送事件信号。 该单元被配置为接收到包括该单元的总线斜坡的基地址的配置信号。 通过调整配置信号中的位域的长度，可灵活选择多个单元和多个监控事件。

    SYSTEM AND METHOD FOR DISTRIBUTING SIGNAL WITH EFFICIENCY OVER MICROPROCESSOR
    8.
    发明申请
    SYSTEM AND METHOD FOR DISTRIBUTING SIGNAL WITH EFFICIENCY OVER MICROPROCESSOR 失效
    通过微处理器分发信号的效率的系统和方法

    公开(公告)号：US20100161867A1

    公开(公告)日：2010-06-24

    申请号：US12343594

    申请日：2008-12-24

    申请人： Matthias Fertig ,  Tilman Gloekler ,  Ralph C. Koester ,  Alexander Erik Mericas ,  Thomas Pflueger

    发明人： Matthias Fertig ,  Tilman Gloekler ,  Ralph C. Koester ,  Alexander Erik Mericas ,  Thomas Pflueger

    IPC分类号： G06F13/36

    CPC分类号： G06F13/4247 ,  G06F11/3466 ,  G06F11/348 ,  G06F11/349 ,  G06F2201/88

    摘要： A system and associated method for distributing signals with efficiency over a microprocessor. A performance monitoring unit (PMU) sends configuration signals to a unit to monitor an event occurring on the unit. The unit is attached to a configuration bus and an event bus that are daisy-chained from PMU to other units in the microprocessor. The configuration bus transmits configuration signals from the PMU to the unit to set the unit to report the event. The unit sends event signals to the PMU through the event bus. The unit is configured upon receiving configuration signals comprising a base address of a bus ramp of the unit. A number of units and a number of events for monitoring is flexibly selected by adjusting a length of bit fields within configuration signals.

    摘要翻译： 一种用于通过微处理器分配信号的系统和相关方法。 性能监控单元（PMU）将配置信号发送到单元以监视本机发生的事件。 该单元连接到配置总线和从PMU菊花链到微处理器中的其他单元的事件总线。 配置总线将配置信号从PMU发送到单元以设置单元以报告事件。 该单元通过事件总线向PMU发送事件信号。 该单元被配置为接收到包括该单元的总线斜坡的基地址的配置信号。 通过调整配置信号中的位域的长度，可灵活选择多个单元和多个监控事件。

    SECURE POWER-ON RESET ENGINE
    9.
    发明申请
    SECURE POWER-ON RESET ENGINE 失效
    安全上电复位发动机

    公开(公告)号：US20090055637A1

    公开(公告)日：2009-02-26

    申请号：US11844449

    申请日：2007-08-24

    申请人： Ingemar Holm ,  Ralph C. Koester ,  Cedric Lichtenau ,  Thomas Pflueger ,  Mack W. Riley

    发明人： Ingemar Holm ,  Ralph C. Koester ,  Cedric Lichtenau ,  Thomas Pflueger ,  Mack W. Riley

    IPC分类号： G06F15/177

    CPC分类号： G06F21/575 ,  G06F21/71

    摘要： A secure Power-on Reset (POR) engine is provided, inside a processor chip, which guarantees a secure initialization of the chip to enable secure code execution. External access to chip resources is limited to a very few targeted settings that do not compromise the chip security. The POR engine comprises a small state machine that runs through a predefined sequence coded in persistent memory contained in the processor chip. The state machine initializes the chip and allows external access from an external processor to only some scan chains of the processor chip in order to configure interfaces, and the like, without compromising the chip security. The state machine also manages the encryption keys that are used to verify that the code, fetched by the processor to complete the initialization in software, is not modified by a third party.

    摘要翻译： 在处理器芯片内提供安全的上电复位（POR）引擎，保证了芯片的安全初始化，从而实现安全的代码执行。 对芯片资源的外部访问仅限于不损害芯片安全性的极少量目标设置。 POR引擎包括一个小型状态机，其运行在包含在处理器芯片中的持久存储器中编码的预定义序列。 状态机初始化芯片，并且允许从外部处理器到处理器芯片的一些扫描链的外部访问，以便配置接口等，而不损害芯片的安全性。 状态机还管理加密密钥，用于验证由处理器获取的以软件完成初始化的代码不被第三方修改。

    Secure power-on reset engine
    10.
    发明授权
    Secure power-on reset engine 失效
    安全上电复位引擎

    公开(公告)号：US07895426B2

    公开(公告)日：2011-02-22

    申请号：US11844449

    申请日：2007-08-24

    申请人： Ingemar Holm ,  Ralph C. Koester ,  Cedric Lichtenau ,  Thomas Pflueger ,  Mack W. Riley

    发明人： Ingemar Holm ,  Ralph C. Koester ,  Cedric Lichtenau ,  Thomas Pflueger ,  Mack W. Riley

    IPC分类号： G06F9/00 ,  G06F13/00 ,  H03L7/00

    CPC分类号： G06F21/575 ,  G06F21/71

    摘要： A secure Power-on Reset (POR) engine is provided, inside a processor chip, which guarantees a secure initialization of the chip to enable secure code execution. External access to chip resources is limited to a very few targeted settings that do not compromise the chip security. The POR engine comprises a small state machine that runs through a predefined sequence coded in persistent memory contained in the processor chip. The state machine initializes the chip and allows external access from an external processor to only some scan chains of the processor chip in order to configure interfaces, and the like, without compromising the chip security. The state machine also manages the encryption keys that are used to verify that the code, fetched by the processor to complete the initialization in software, is not modified by a third party.

    摘要翻译： 在处理器芯片内提供安全的上电复位（POR）引擎，保证了芯片的安全初始化，从而实现安全的代码执行。 对芯片资源的外部访问仅限于不损害芯片安全性的极少量目标设置。 POR引擎包括一个小型状态机，其运行在包含在处理器芯片中的持久存储器中编码的预定义序列。 状态机初始化芯片，并且允许从外部处理器到处理器芯片的一些扫描链的外部访问，以便配置接口等，而不损害芯片的安全性。 状态机还管理加密密钥，用于验证由处理器获取的以软件完成初始化的代码不被第三方修改。