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1.发明申请SYSTEM AND METHOD FOR DISTRIBUTING SIGNAL WITH EFFICIENCY OVER MICROPROCESSOR 失效通过微处理器分发信号的效率的系统和方法公开(公告)号：US20100161867A1
公开(公告)日：2010-06-24
申请号：US12343594
申请日：2008-12-24
申请人： Matthias Fertig , Tilman Gloekler , Ralph C. Koester , Alexander Erik Mericas , Thomas Pflueger
发明人： Matthias Fertig , Tilman Gloekler , Ralph C. Koester , Alexander Erik Mericas , Thomas Pflueger
IPC分类号： G06F13/36
CPC分类号： G06F13/4247 , G06F11/3466 , G06F11/348 , G06F11/349 , G06F2201/88
摘要： A system and associated method for distributing signals with efficiency over a microprocessor. A performance monitoring unit (PMU) sends configuration signals to a unit to monitor an event occurring on the unit. The unit is attached to a configuration bus and an event bus that are daisy-chained from PMU to other units in the microprocessor. The configuration bus transmits configuration signals from the PMU to the unit to set the unit to report the event. The unit sends event signals to the PMU through the event bus. The unit is configured upon receiving configuration signals comprising a base address of a bus ramp of the unit. A number of units and a number of events for monitoring is flexibly selected by adjusting a length of bit fields within configuration signals.
摘要翻译： 一种用于通过微处理器分配信号的系统和相关方法。 性能监控单元（PMU）将配置信号发送到单元以监视本机发生的事件。 该单元连接到配置总线和从PMU菊花链到微处理器中的其他单元的事件总线。 配置总线将配置信号从PMU发送到单元以设置单元以报告事件。 该单元通过事件总线向PMU发送事件信号。 该单元被配置为接收到包括该单元的总线斜坡的基地址的配置信号。 通过调整配置信号中的位域的长度，可灵活选择多个单元和多个监控事件。
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2.发明授权公开(公告)号：US08055809B2
公开(公告)日：2011-11-08
申请号：US12343594
申请日：2008-12-24
申请人： Matthias Fertig , Tilman Gloekler , Ralph C. Koester , Alexander Erik Mericas , Thomas Pflueger , Daniel Becker
发明人： Matthias Fertig , Tilman Gloekler , Ralph C. Koester , Alexander Erik Mericas , Thomas Pflueger , Daniel Becker
IPC分类号： G06F3/00
CPC分类号： G06F13/4247 , G06F11/3466 , G06F11/348 , G06F11/349 , G06F2201/88
摘要： A system and associated method for distributing signals with efficiency over a microprocessor. A performance monitoring unit (PMU) sends configuration signals to a unit to monitor an event occurring on the unit. The unit is attached to a configuration bus and an event bus that are daisy-chained from PMU to other units in the microprocessor. The configuration bus transmits configuration signals from the PMU to the unit to set the unit to report the event. The unit sends event signals to the PMU through the event bus. The unit is configured upon receiving configuration signals comprising a base address of a bus ramp of the unit. A number of units and a number of events for monitoring is flexibly selected by adjusting a length of bit fields within configuration signals.
摘要翻译： 一种用于通过微处理器分配信号的系统和相关方法。 性能监视单元（PMU）将配置信号发送到单元以监视本机发生的事件。 该单元连接到配置总线和从PMU菊花链到微处理器中的其他单元的事件总线。 配置总线将配置信号从PMU发送到单元以设置单元以报告事件。 该单元通过事件总线向PMU发送事件信号。 该单元被配置为接收到包括该单元的总线斜坡的基地址的配置信号。 通过调整配置信号中的位域的长度，可灵活选择多个单元和多个监控事件。
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3.发明申请Method and an Arrangement for Arbitrating Requests to Grant Access to Shared Resources 审中-公开仲裁请求获得共享资源的方法和安排公开(公告)号：US20080172508A1
公开(公告)日：2008-07-17
申请号：US11972648
申请日：2008-01-11
申请人： Tilman Gloekler , Thuyen Le , Thomas Pflueger , Matthias Woehrlc
发明人： Tilman Gloekler , Thuyen Le , Thomas Pflueger , Matthias Woehrlc
IPC分类号： G06F13/372
CPC分类号： G06F13/372
摘要： The present invention relates to a method for arbitrating requests from masters to grant access to shared resources, wherein each master has an individual weight. The method comprises the steps of assigning time slots to the masters depending on the weights of the masters, mapping the current time slot index (32) to a reordering index (30), receiving a plurality of requests from N masters, reordering the requests into a request vector (14) depending on the reordering index (30), searching for predetermined logical values in the request vector (14), generating a grant vector (18) according to the index of the found logical values in the request vector (14), inversely reordering the grant vector (18) into an output grant vector (22) depending on the reordering index (30), and calculating a new time slot index (32) on the basis of the current time slot index (30) and the grant vector (18). Further the present invention relates to a system for performing the method.
摘要翻译： 本发明涉及一种用于仲裁主人的请求以授权对共享资源的访问的方法，其中每个主人具有单独的权重。 该方法包括以下步骤：根据主机的权重向主机分配时隙，将当前时隙索引（32）映射到重新排序索引（30），从N个主机接收多个请求，将请求重新排序 根据重新排序索引（30）的请求向量（14），在请求向量（14）中搜索预定的逻辑值，根据请求向量（14）中找到的逻辑值的索引生成授权向量（18） ），根据所述重排序索引（30）将所述授权向量（18）逆序排列到输出许可向量（22）中，并且基于当前时隙索引（30）计算新的时隙索引（32），以及 授权向量（18）。 此外，本发明涉及一种用于执行该方法的系统。
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公开(公告)号：US08719607B2
公开(公告)日：2014-05-06
申请号：US13308884
申请日：2011-12-01
CPC分类号： G06F1/3293 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A mechanism for power management of processors using Pstates is provided. In a chiplet of a processor in a data processing system, a request is received to change a Pstate from a current Pstate to a requested Pstate. A determination is made as to whether the requested Pstate is less than or equal to a maximum Pstate. Responsive to the requested Pstate being less than or equal to the maximum Pstate, a frequency associated with the requested Pstate is computed thereby forming a computed frequency. An operating frequency of the chiplet is then adjusted to the computed frequency without involvement from a central power control entity.
摘要翻译： 提供了使用Pstates处理器进行电源管理的机制。 在数据处理系统中的处理器的小灯中，接收到将Pstate从当前Pstate更改为所请求的Pstate的请求。 确定所请求的Pstate是否小于或等于最大Pstate。 响应于所请求的Pstate小于或等于最大Pstate，计算与所请求的Pstate相关联的频率，从而形成计算出的频率。 然后将小灯的工作频率调整到计算出的频率，而不受中央功率控制实体的参与。
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公开(公告)号：US20130145188A1
公开(公告)日：2013-06-06
申请号：US13308884
申请日：2011-12-01
IPC分类号： G06F1/32
CPC分类号： G06F1/3293 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： A mechanism for power management of processors using Pstates is provided. In a chiplet of a processor in a data processing system, a request is received to change a Pstate from a current Pstate to a requested Pstate. A determination is made as to whether the requested Pstate is less than or equal to a maximum Pstate. Responsive to the requested Pstate being less than or equal to the maximum Pstate, a frequency associated with the requested Pstate is computed thereby forming a computed frequency. An operating frequency of the chiplet is then adjusted to the computed frequency without involvement from a central power control entity.
摘要翻译： 提供了使用Pstates处理器进行电源管理的机制。 在数据处理系统中的处理器的小灯中，接收到将Pstate从当前Pstate更改为所请求的Pstate的请求。 确定所请求的Pstate是否小于或等于最大Pstate。 响应于所请求的Pstate小于或等于最大Pstate，计算与所请求的Pstate相关联的频率，从而形成计算出的频率。 然后将小灯的工作频率调整到计算出的频率，而不受中央功率控制实体的参与。
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公开(公告)号：US20090055637A1
公开(公告)日：2009-02-26
申请号：US11844449
申请日：2007-08-24
IPC分类号： G06F15/177
CPC分类号： G06F21/575 , G06F21/71
摘要： A secure Power-on Reset (POR) engine is provided, inside a processor chip, which guarantees a secure initialization of the chip to enable secure code execution. External access to chip resources is limited to a very few targeted settings that do not compromise the chip security. The POR engine comprises a small state machine that runs through a predefined sequence coded in persistent memory contained in the processor chip. The state machine initializes the chip and allows external access from an external processor to only some scan chains of the processor chip in order to configure interfaces, and the like, without compromising the chip security. The state machine also manages the encryption keys that are used to verify that the code, fetched by the processor to complete the initialization in software, is not modified by a third party.
摘要翻译： 在处理器芯片内提供安全的上电复位（POR）引擎，保证了芯片的安全初始化，从而实现安全的代码执行。 对芯片资源的外部访问仅限于不损害芯片安全性的极少量目标设置。 POR引擎包括一个小型状态机，其运行在包含在处理器芯片中的持久存储器中编码的预定义序列。 状态机初始化芯片，并且允许从外部处理器到处理器芯片的一些扫描链的外部访问，以便配置接口等，而不损害芯片的安全性。 状态机还管理加密密钥，用于验证由处理器获取的以软件完成初始化的代码不被第三方修改。
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公开(公告)号：US07895426B2
公开(公告)日：2011-02-22
申请号：US11844449
申请日：2007-08-24
CPC分类号： G06F21/575 , G06F21/71
摘要： A secure Power-on Reset (POR) engine is provided, inside a processor chip, which guarantees a secure initialization of the chip to enable secure code execution. External access to chip resources is limited to a very few targeted settings that do not compromise the chip security. The POR engine comprises a small state machine that runs through a predefined sequence coded in persistent memory contained in the processor chip. The state machine initializes the chip and allows external access from an external processor to only some scan chains of the processor chip in order to configure interfaces, and the like, without compromising the chip security. The state machine also manages the encryption keys that are used to verify that the code, fetched by the processor to complete the initialization in software, is not modified by a third party.
摘要翻译： 在处理器芯片内提供安全的上电复位（POR）引擎，保证了芯片的安全初始化，从而实现安全的代码执行。 对芯片资源的外部访问仅限于不损害芯片安全性的极少量目标设置。 POR引擎包括一个小型状态机，其运行在包含在处理器芯片中的持久存储器中编码的预定义序列。 状态机初始化芯片，并且允许从外部处理器到处理器芯片的一些扫描链的外部访问，以便配置接口等，而不损害芯片的安全性。 状态机还管理加密密钥，用于验证由处理器获取的以软件完成初始化的代码不被第三方修改。
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公开(公告)号：US07880207B2
公开(公告)日：2011-02-01
申请号：US12350991
申请日：2009-01-09
IPC分类号： H01L31/113
CPC分类号： H01L27/14692 , H01L27/1462
摘要： A photo detector device comprising a first layer comprising a first material, and a second layer arranged adjacent to the first layer, the second layer comprising strained silicon, wherein the second layer further comprises a light absorption region located substantially within the strained silicon, wherein the first or the second layer is arranged on a substrate.
摘要翻译： 一种光检测器装置，包括包含第一材料的第一层和邻近第一层布置的第二层，第二层包括应变硅，其中第二层还包括基本上位于应变硅内的光吸收区，其中， 第一层或第二层被布置在基板上。
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9.发明授权公开(公告)号：US08225241B2
公开(公告)日：2012-07-17
申请号：US12267820
申请日：2008-11-10
申请人： Matthias Fertig , Nikolaj Moll , Thomas E. Morf , Thomas Pflueger
发明人： Matthias Fertig , Nikolaj Moll , Thomas E. Morf , Thomas Pflueger
IPC分类号： G06F17/50
CPC分类号： H01L31/105 , B82Y20/00 , G02F1/015 , G02F1/01708 , G02F2001/0154 , G02F2201/124 , G02F2201/305 , H04N21/23424 , H04N21/42202 , H04N21/44016 , H04N21/44218
摘要： A method and apparatus for designing a device to operate in a coupling mode, a detection mode, or a reflection mode for incident light. The incident light has a wavelength λ and is incident upon a semiconductor structure of the device at an angle of incidence (θi). A voltage (V) is applied to the device. Each mode may be designed for an ON state and/or OFF state. For the coupling mode and detection mode, the ON state and OFF state is characterized by high and low absorption of the incident light, respectively, by the semiconductor structure in conjunction with the applied voltage V and angle of incidence θi. For the reflection mode, the OFF state and ON states is characterized by a shift in the optical path length of λ/2 and about zero, respectively, in conjunction with the applied voltage V and angle of incidences θi.
摘要翻译： 一种用于设计在入射光的耦合模式，检测模式或反射模式下工作的装置的方法和装置。 入射光具有波长λ并且以入射角入射到器件的半导体结构（I）上。 电压（V）被施加到器件。 每个模式可以被设计为ON状态和/或OFF状态。 对于耦合模式和检测模式，ON状态和OFF状态的特征在于分别由半导体结构与施加的电压V和入射角相关的入射光的高吸收和低吸收; i。 对于反射模式，关断状态和导通状态的特征在于分别与施加的电压V和发生角度的角度相关联的λ/ 2的光程长度和大约零的偏移; i。
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公开(公告)号：US20090179225A1
公开(公告)日：2009-07-16
申请号：US12350991
申请日：2009-01-09
IPC分类号： H01L31/0256 , H01L21/20
CPC分类号： H01L27/14692 , H01L27/1462
摘要： A photo detector device comprising a first layer comprising a first material, and a second layer arranged adjacent to the first layer, the second layer comprising strained silicon, wherein the second layer further comprises a light absorption region located substantially within the strained silicon, wherein the first or the second layer is arranged on a substrate.
摘要翻译： 一种光检测器装置，包括包含第一材料的第一层和邻近第一层布置的第二层，第二层包括应变硅，其中第二层还包括基本上位于应变硅内的光吸收区，其中， 第一层或第二层被布置在基板上。
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