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公开(公告)号：US5880983A
公开(公告)日：1999-03-09
申请号：US620733
申请日：1996-03-25
CPC分类号： G06F7/5443 , G06F7/483 , G06F7/49942
摘要： A method and system for an infinite precision split multiply and add operation which has increased speed. The method and system for providing a split multiply and add of a plurality of operands include a multiplier and an adder means. The multiplier multiplies a first portion of the plurality of operands, thereby providing a product. The adder, which combines the remaining operands and the product, comprise at least one pair of data paths. Each pair of data paths comprises a first data path and a second data path. The first data path comprises a first aligner, a first adder, and a first normalizer capable of shifting a mantissa by a substantially fewer number digits than the aligner. The second data path comprises a second aligner, a second adder, and a second normalizer capable of shifting a mantissa by a substantially larger number of digits than the aligner. Accordingly, the present invention includes split multiply and add data paths which, individually, are faster than a fused multiply and add. In addition, the split multiply and add data paths can preserve the appearance of infinite precision. Consequently, overall system performance is increased.
摘要翻译： 一种用于无限精密分割乘法和加法运算的方法和系统，其具有增加的速度。 用于提供多个操作数的分割乘法和相加的方法和系统包括乘法器和加法器装置。 乘法器乘以多个操作数的第一部分，从而提供乘积。 组合剩余操作数和乘积的加法器包括至少一对数据路径。 每对数据路径包括第一数据路径和第二数据路径。 第一数据路径包括第一对准器，第一加法器和第一归一化器，其能够将尾数与对准器相比更少的数字位移。 第二数据路径包括第二对准器，第二加法器和第二归一化器，其能够将尾数移位比对准器大得多的位数。 因此，本发明包括分离的乘法和加法数据路径，其分别比融合乘法和加法更快。 此外，拆分乘法和添加数据路径可以保持无限精度的外观。 因此，整体系统性能提高。
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2.发明授权
公开(公告)号：US5790445A
公开(公告)日：1998-08-04
申请号：US641307
申请日：1996-04-30
摘要： A system and method for calculating a floating point add/subtract of a plurality of floating point operands is disclosed. The system comprises at least one pair of data paths. Each pair of data paths comprises a first data path and a second data path. The first data path includes a first aligner, a first adder coupled to the first aligner, and a first normalizer coupled to the first adder. The first normalizer is capable of shifting a mantissa by a substantially smaller number of digits than the first aligner. The second data path comprises control logic, a second aligner coupled to the control logic, a second adder coupled to the second aligner, and a second normalizer coupled to the second adder. The control logic provides a control signal that is responsive to a first predetermined number of digits of each exponent of a pair of exponents. The pair of exponents are the exponents for a pair of inputs to the second data path. The second aligner is responsive to the control signal provided by the control logic. In addition, the second normalizer is capable of shifting a mantissa by a substantially larger number of digits than the second aligner.
摘要翻译： 公开了一种用于计算多个浮点操作数的浮点加法/减法的系统和方法。 该系统包括至少一对数据路径。 每对数据路径包括第一数据路径和第二数据路径。 第一数据路径包括第一对准器，耦合到第一对准器的第一加法器和耦合到第一加法器的第一归一化器。 第一标准器能够将尾数移位比第一对准器小得多的位数。 第二数据路径包括控制逻辑，耦合到控制逻辑的第二对准器，耦合到第二对准器的第二加法器以及耦合到第二加法器的第二归一化器。 控制逻辑提供响应于一对指数的每个指数的第一预定数量位数的控制信号。 一对指数是对于第二数据路径的一对输入的指数。 第二对准器响应于由控制逻辑提供的控制信号。 此外，第二归一化器能够将尾数移动比第二对准器大得多的位数。
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3.发明授权System for reordering of instructions before placement into cache to reduce dispatch latency 失效在放入缓存之前重新排序指令的系统，以减少调度延迟
公开(公告)号：US5742784A
公开(公告)日：1998-04-21
申请号：US377976
申请日：1995-01-25
CPC分类号： G06F9/3802 , G06F9/3853
摘要： A method and system for reducing the dispatch latency of instructions of a processor provides for reordering the instructions in a predetermined format before the instructions enter the cache. The method and system also stores information in the cache relating to the reordering of the instructions. The reordered instructions are then provided to the appropriate execution units based upon the predetermined format. With this system, a dispatch buffer is not required when sending the instructions to the cache.
摘要翻译： 用于减少处理器的指令的调度等待时间的方法和系统提供在指令进入高速缓存之前以预定格式重新排序指令。 方法和系统还将信息存储在与指令的重新排序相关的缓存中。 然后，基于预定格式将重排序的指令提供给适当的执行单元。 使用该系统，在向缓存发送指令时不需要调度缓冲区。
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4.发明授权Method and system for high performance dynamic and user programmable cache arbitration 失效高性能动态和用户可编程高速缓存仲裁的方法和系统
公开(公告)号：US5822758A
公开(公告)日：1998-10-13
申请号：US709793
申请日：1996-09-09
CPC分类号： G06F12/0897 , G06F13/18
摘要： A system and method for improving arbitration of a plurality of events that may require access to a cache is disclosed. In a first aspect, the method and system provide dynamic arbitration. The first aspect comprises first logic for determining whether at least one of the plurality of events requires access to the cache and for outputting at least one signal in response thereto. Second logic coupled to the first logic determines the priority of each of the plurality of events in response to the at least one signal and outputs a second signal specifying the priority of each event. Third logic coupled to the second logic grants access to the cache in response to the second signal. A second aspect of the method and system provides user programmable arbitration. The second aspect comprises a storage unit which allows the user to input information indicating the priority of at least one of the plurality of events and outputs a first signal in response to the information. In the second aspect, first logic coupled to the storage unit determines the priority of each of the plurality of events in response to the first signal and outputs a second signal indicating the priority of each event. Second logic coupled to the first logic grants access to the cache in response to the second signal.
摘要翻译： 公开了一种用于改善可能需要访问高速缓存的多个事件的仲裁的系统和方法。 在第一方面，该方法和系统提供动态仲裁。 第一方面包括用于确定多个事件中的至少一个是否需要访问高速缓冲存储器并且响应于此来输出至少一个信号的第一逻辑。 耦合到第一逻辑的第二逻辑响应于至少一个信号确定多个事件中的每一个的优先级，并且输出指定每个事件的优先级的第二信号。 耦合到第二逻辑的第三逻辑响应于第二信号而允许对高速缓存的访问。 该方法和系统的第二方面提供用户可编程仲裁。 第二方面包括存储单元，其允许用户输入指示多个事件中的至少一个的优先级的信息，并且响应于该信息输出第一信号。 在第二方面，耦合到存储单元的第一逻辑响应于第一信号确定多个事件中的每一个的优先级，并且输出指示每个事件的优先级的第二信号。 耦合到第一逻辑的第二逻辑响应于第二信号而允许对高速缓存的访问。
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公开(公告)号：US5805487A
公开(公告)日：1998-09-08
申请号：US677843
申请日：1996-07-12
CPC分类号： G06F7/483 , G06F7/49952 , G06F7/49957
摘要： A method and system for fast calculation of the sticky bit and a function of the guard bit is disclosed. A first aspect of the method and system provides a fast calculation of the sticky bit. A second aspect provides a fast calculation of a function of the guard bit. Both aspects comprise means for providing an intermediate result of a floating point mathematical operation involving at least a first and a second operand and means for providing a mask indicating a position of a leading one in a mantissa of the intermediate result. In the first aspect, means for aligning a first bit of the mask to an (n+2)nd bit of the intermediate result, where n is the number of bits in a mantissa of the first or second operand, are coupled to the intermediate result providing means. In the second aspect, means for aligning a first bit of the mask to an (n+1)st bit of the intermediate result are coupled to the intermediate result providing means. In both aspects, means for providing an output are coupled to the aligning means and intermediate result providing means. The output of the first aspect comprises the sticky bit. The output of the second aspect comprises a function of the guard bit. Thus, the method and system allow the sticky bit and a function of the guard bit to be calculated substantially simultaneously with normalization. Because the method and system allow fast determination of the sticky bit and a function of the guard bit, the overall speed of the calculation is increased and system performance is improved.
摘要翻译： 公开了一种用于快速计算粘滞位和保护位功能的方法和系统。 该方法和系统的第一方面提供了粘性位的快速计算。 第二方面提供了对保护位的功能的快速计算。 两个方面包括用于提供涉及至少第一和第二操作数的浮点数学运算的中间结果的装置，以及用于提供指示中间结果的尾数中的前导位置的掩码的装置。 在第一方面，用于将掩模的第一位与中间结果的第（n + 2）位对齐的装置，其中n是第一或第二操作数的尾数中的位数， 结果提供手段。 在第二方面，用于将掩模的第一位与中间结果的第（n + 1）位进行对准的装置耦合到中间结果提供装置。 在两个方面，用于提供输出的装置耦合到对准装置和中间结果提供装置。 第一方面的输出包括粘点。 第二方面的输出包括保护位的功能。 因此，该方法和系统允许基本上与归一化同时计算粘滞位和保护位的功能。 由于方法和系统允许快速确定粘滞位和保护位的功能，所以计算的总速度提高，系统性能得到提高。
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