公开(公告)号：US20130013656A1

公开(公告)日：2013-01-10

申请号：US13178508

申请日：2011-07-08

申请人： Timothy D. Anderson ,  Mujibur Rahman ,  Kai Chirca

发明人： Timothy D. Anderson ,  Mujibur Rahman ,  Kai Chirca

IPC分类号： G06F7/503

CPC分类号： G06F7/57 ,  G06F7/5055 ,  G06F7/506

摘要： A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B−2k.

摘要翻译： 预测加法器产生将形式为2k的1比特常数递增和/或递减A和B的和的结果，其中k是要递增或递减的比特位置。 预测加法器预测第一操作数A和第二操作数B的电位之和的纹波部分，该第一操作数A和第二操作数B将通过将和A + B递增或递减1比特常数来切换，以产生和指示纹波部分 的位数在电位和。 预测加法器使用电位和中的波纹部分的指示和通过评估A + B产生的进位输出来产生A + B + 2k和A + B-2k中的至少一个的结果。

公开(公告)号：US08713086B2

公开(公告)日：2014-04-29

申请号：US13178508

申请日：2011-07-08

申请人： Timothy D. Anderson ,  Mujibur Rahman ,  Kai Chirca

发明人： Timothy D. Anderson ,  Mujibur Rahman ,  Kai Chirca

IPC分类号： G06F7/50

CPC分类号： G06F7/57 ,  G06F7/5055 ,  G06F7/506

摘要： A predictive adder produces the result of incrementing and/or decrementing a sum of A and B by a one-bit constant of the form of the form 2k, where k is a bit position at which the sum is to be incremented or decremented. The predictive adder predicts the ripple portion of bits in the potential sum of the first operand A and the second operand B that would be toggled by incrementing or decrementing the sum A+B by the one-bit constant to generate and indication of the ripple portion of bits in the potential sum. The predictive adder uses the indication of the ripple portion of bits in the potential sum and the carry output generated by evaluating A+B to produce the results of at least one of A+B+2k and A+B−2k.

摘要翻译： 预测加法器产生将形式为2k的1比特常数递增和/或递减A和B的和的结果，其中k是要递增或递减的比特位置。 预测加法器预测第一操作数A和第二操作数B的电位之和的纹波部分，该第一操作数A和第二操作数B将通过将和A + B递增或递减1比特常数来切换，以产生和指示纹波部分 的位数在电位和。 预测加法器使用电位和中的波纹部分的指示和通过评估A + B产生的进位输出来产生A + B + 2k和A + B-2k中的至少一个的结果。

公开(公告)号：US08706940B2

公开(公告)日：2014-04-22

申请号：US13210732

申请日：2011-08-16

申请人： Kai Chirca ,  Timothy D. Anderson

发明人： Kai Chirca ,  Timothy D. Anderson

IPC分类号： G06F12/00

CPC分类号： G06F13/1663

摘要： Multiprocessor systems often share access to a centralized memory and experience conflicting access requests. An arbitration unit mediates priorities of requestor preferably ensuring both priority and fairness. In this invention upon an access conflict the arbitrator grants access to one requestor having the highest priority level and stalls other conflicting requestors. If plural requestors have the same priority level, the arbiter grants access to one and stalls the others. The arbiter then adjusts the priority levels of the requestors. The priority of the requestor granted access is decreased by the number of stalled requestors. The stalled requestors have their priority levels increased by one. The arbitration decision is thus based on the stall history and the caused stall history of each requestor.

摘要翻译： 多处理器系统通常共享对集中式内存的访问，并且会遇到冲突的访问请求。 仲裁单位调解请求者的优先级，最好确保优先级和公平性。 在本发明中，当访问冲突时，仲裁者授予对具有最高优先级的一个请求者的访问，并且阻止其他冲突的请求者。 如果多个请求者具有相同的优先级，则仲裁者授予访问权限并使其他人失效。 仲裁器然后调整请求者的优先级。 请求者授予访问权限的优先级减少了停滞请求者的数量。 被拖延的请求者的优先级别增加了1。 因此，仲裁决定基于每个请求者的失速历史和引起的失速历史。

公开(公告)号：US08473689B2

公开(公告)日：2013-06-25

申请号：US12843980

申请日：2010-07-27

申请人： Timothy D. Anderson ,  Kai Chirca

发明人： Timothy D. Anderson ,  Kai Chirca

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F2212/6022 ,  G06F2212/6026

摘要： A system for prefetching memory in caching systems includes a processor that generates requests for data. A cache of a first level stores memory lines retrieved from a lower level memory in response to references to addresses generated by the processor's requests for data. A prefetch buffer is used to prefetch an adjacent memory line from the lower level memory in response to a request for data. The adjacent memory line is a memory line that is adjacent to a first memory line that is associated with an address of the request for data. An indication that a memory line associated with an address associated with the requested data has been prefetched is stored. A prefetched memory line is transferred to the cache of the first level in response to the stored indication that a memory line associated with an address associated with the requested data has been prefetched.

摘要翻译： 用于在高速缓存系统中预取存储器的系统包括产生数据请求的处理器。 响应于对由处理器对数据请求产生的地址的引用，第一级缓存存储从较低级存储器检索的存储器线。 响应于对数据的请求，预取缓冲器用于从低级存储器预取相邻存储器行。 相邻存储器线是与与数据请求的地址相关联的第一存储器线相邻的存储器线。 存储与已经预取的与所请求的数据相关联的地址相关联的存储器线的指示。 响应于存储的指示已经预取与与所请求的数据相关联的地址相关联的存储器线路，预取存储器线路被传送到第一级的高速缓存。

公开(公告)号：US20120072796A1

公开(公告)日：2012-03-22

申请号：US13237917

申请日：2011-09-20

申请人： Kai Chirca ,  Timothy D. Anderson ,  Amitabh Menon

发明人： Kai Chirca ,  Timothy D. Anderson ,  Amitabh Menon

IPC分类号： G11C29/04 ,  G06F11/16

CPC分类号： G06F12/0897 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3844 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0886 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6028

摘要： A memory validation manager reserves a block of time for exclusive accesses to a memory bank having lines of memory for which validation codes provide a degree of error detection and correction for each memory line. The memory validation manager reads, processes, and corrects at least some of the contents of each memory line based on indications of validity encountered for each memory line. New data is written in response to a validation code. Likewise, a valid field for each line can be updated and a new validation code written for a memory when the valid field indicates that a validation code has not yet been written for a memory line. The memory validation manager processes data read from a first memory line while either reading or writing to another memory line to minimize the latency of the process of scrubbing memory lines.

摘要翻译： 存储器验证管理器保留一段时间来独占访问具有存储线的存储器，其中验证码为每个存储器线提供一定程度的错误检测和校正。 存储器验证管理器基于每个存储器线遇到的有效性的指示来读取，处理和校正每个存储器行的至少一些内容。 新数据是响应验证码而编写的。 同样，当有效字段指示还没有为存储器行写入验证码时，可以更新每一行的有效字段和为存储器编写的新验证码。 存储器验证管理器处理从第一存储器线读取的数据，同时读取或写入另一存储器线以最小化擦除存储器线的过程的延迟。

公开(公告)号：US09239798B2

公开(公告)日：2016-01-19

申请号：US13233028

申请日：2011-09-15

申请人： Matthew D Pierson ,  Joseph R M Zbiciak ,  Kai Chirca ,  Amitabh Menon ,  Timothy D Anderson

发明人： Matthew D Pierson ,  Joseph R M Zbiciak ,  Kai Chirca ,  Amitabh Menon ,  Timothy D Anderson

IPC分类号： G06F12/00 ,  G06F12/08 ,  G06F9/38

CPC分类号： G06F12/0897 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3844 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0886 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6028

摘要： A prefetch cancelation arbiter improves access to a shared memory resource by arbitrarily canceling speculative prefetches. The prefetch cancelation arbiter applies a set of arbitrary policies to speculative prefetches to select one or more of the received speculative prefetches to cancel. The selected speculative prefetches are canceled and a cancelation notification of each canceled speculative prefetch is sent to a higher-level memory component such as a prefetch unit or a local memory arbiter that is local to the processor associated with the canceled speculative prefetch. The set of arbitrary policies is used to reduce memory accesses to the shared memory resource.

摘要翻译： 预取消除仲裁器通过任意取消推测性预取来改善对共享存储器资源的访问。 预取消除仲裁器将一组任意策略应用于推测预取以选择一个或多个接收到的推测性预取以取消。 所选择的推测预取被取消，并且每个取消的推测预取的取消通知被发送到诸如与取消的推测预取相关联的处理器本地的预取单元或本地存储器仲裁器的更高级存储器组件。 该组任意策略用于减少对共享内存资源的内存访问。

公开(公告)号：US08706969B2

公开(公告)日：2014-04-22

申请号：US13218394

申请日：2011-08-25

申请人： Timothy D Anderson ,  Kai Chirca

发明人： Timothy D Anderson ,  Kai Chirca

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34

CPC分类号： G06F12/0897 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3844 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0886 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6028

摘要： A prefetch unit generates prefetch addresses in response to an initial received memory read request, an address associated with the initial received memory read request, a line length of the requestor of the initial received memory read request, and a request type width of the initial received memory read request. Prefetch operations are generated using the generated prefetch addresses, wherein each generated prefetch address is stored in a prefetch buffer slot that is selected by a prefetch FIFO (First In First Out) prefetch counter. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.

摘要翻译： 预取单元响应于初始接收到的存储器读取请求，与初始接收到的存储器读取请求相关联的地址，初始接收存储器读取请求的请求者的行长度以及初始接收到的存储器读取请求的请求类型宽度来生成预取地址 内存读取请求。 使用生成的预取地址生成预取操作，其中每个生成的预取地址被存储在由预取FIFO（先进先出）预取计数器选择的预取缓冲器槽中。 在预取器上的后续命中导致响应于在初始接收到的存储器读取请求之后接收到的后续存储器读取请求而将预取数据返回给请求者。

公开(公告)号：US20120072667A1

公开(公告)日：2012-03-22

申请号：US13218394

申请日：2011-08-25

申请人： Timothy D. Anderson ,  Kai Chirca

发明人： Timothy D. Anderson ,  Kai Chirca

IPC分类号： G06F12/08

CPC分类号： G06F12/0897 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3844 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0886 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6028

摘要： A prefetch unit generates prefetch addresses in response to an initial received memory read request, an address associated with the initial received memory read request, a line length of the requestor of the initial received memory read request, and a request type width of the initial received memory read request. Prefetch operations are generated using the generated prefetch addresses, wherein each generated prefetch address is stored in a prefetch buffer slot that is selected by a prefetch FIFO (First In First Out) prefetch counter. Subsequent hits on the prefetcher result in returning prefetched data to the requestor in response to a subsequent memory read request received after the initial received memory read request.

摘要翻译： 预取单元响应于初始接收到的存储器读取请求，与初始接收到的存储器读取请求相关联的地址，初始接收到的存储器读取请求的请求者的行长度以及初始接收的存储器读取请求的请求类型宽度来生成预取地址 内存读取请求。 使用生成的预取地址生成预取操作，其中每个生成的预取地址被存储在由预取FIFO（先进先出）预取计数器选择的预取缓冲器槽中。 在预取器上的后续命中导致响应于在初始接收到的存储器读取请求之后接收到的后续存储器读取请求而将预取数据返回给请求者。

公开(公告)号：US20120030431A1

公开(公告)日：2012-02-02

申请号：US12843980

申请日：2010-07-27

申请人： Timothy D. ANDERSON ,  Kai Chirca

发明人： Timothy D. ANDERSON ,  Kai Chirca

IPC分类号： G06F12/02

CPC分类号： G06F12/0862 ,  G06F2212/6022 ,  G06F2212/6026

摘要： A system for prefetching memory in caching systems includes a processor that generates requests for data. A cache of a first level stores memory lines retrieved from a lower level memory in response to references to addresses generated by the processor's requests for data. A prefetch buffer is used to prefetch an adjacent memory line from the lower level memory in response to a request for data. The adjacent memory line is a memory line that is adjacent to a first memory line that is associated with an address of the request for data. An indication that a memory line associated with an address associated with the requested data has been prefetched is stored. A prefetched memory line is transferred to the cache of the first level in response to the stored indication that a memory line associated with an address associated with the requested data has been prefetched.

摘要翻译： 用于在高速缓存系统中预取存储器的系统包括产生数据请求的处理器。 响应于对由处理器对数据请求产生的地址的引用，第一级缓存存储从较低级存储器检索的存储器线。 响应于对数据的请求，预取缓冲器用于从低级存储器预取相邻存储器行。 相邻存储器线是与与数据请求的地址相关联的第一存储器线相邻的存储器线。 存储与已经预取的与所请求的数据相关联的地址相关联的存储器线的指示。 响应于存储的指示已经预取与与所请求的数据相关联的地址相关联的存储器线路，预取存储器线路被传送到第一级的高速缓存。

公开(公告)号：US08732551B2

公开(公告)日：2014-05-20

申请号：US13237917

申请日：2011-09-20

申请人： Kai Chirca ,  Timothy D. Anderson ,  Amitabh Menon

发明人： Kai Chirca ,  Timothy D. Anderson ,  Amitabh Menon

IPC分类号： G11C29/00

CPC分类号： G06F12/0897 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3844 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0886 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6028

摘要： A memory validation manager reserves a block of time for exclusive accesses to a memory bank having lines of memory for which validation codes provide a degree of error detection and correction for each memory line. The memory validation manager reads, processes, and corrects at least some of the contents of each memory line based on indications of validity encountered for each memory line. New data is written in response to a validation code. Likewise, a valid field for each line can be updated and a new validation code written for a memory when the valid field indicates that a validation code has not yet been written for a memory line. The memory validation manager processes data read from a first memory line while either reading or writing to another memory line to minimize the latency of the process of scrubbing memory lines.

摘要翻译： 存储器验证管理器保留一段时间来独占访问具有存储线的存储器，其中验证码为每个存储器线提供一定程度的错误检测和校正。 存储器验证管理器基于每个存储器线遇到的有效性的指示来读取，处理和校正每个存储器行的至少一些内容。 新数据是响应验证码而编写的。 同样，当有效字段指示还没有为存储器行写入验证码时，可以更新每一行的有效字段和为存储器编写的新验证码。 存储器验证管理器处理从第一存储器线读取的数据，同时读取或写入另一存储器线以最小化擦除存储器线的过程的延迟。