公开(公告)号：US20080093342A1

公开(公告)日：2008-04-24

申请号：US11962271

申请日：2007-12-21

申请人： Timothy Dalton ,  Emily Gallagher ,  Louis Kindt ,  Carey Thiel ,  Andrew Watts

发明人： Timothy Dalton ,  Emily Gallagher ,  Louis Kindt ,  Carey Thiel ,  Andrew Watts

IPC分类号： C23F1/00

CPC分类号： H01J37/32706 ,  H01J37/32091 ,  H01J37/32541

摘要： Method of operating an apparatus which allows etching different substrate etch areas of a substrate having different pattern densities at essentially the same etch rate. The apparatus includes (a) a chamber; (b) an anode and a cathode in the chamber; and (c) a bias power system coupled to the cathode, wherein the cathode includes multiple cathode segments. The operation method is as follows. A substrate to be etched is placed between the anode and cathode, wherein the substrate includes N substrate etch areas, and the N substrate etch areas are directly above the N cathode segments. N bias powers are determined which when being applied to the N cathode segments during an etching of the substrate, will result in essentially a same etch rate for the N substrate etch areas. Then, the bias power system is used to apply the N bias powers the N cathode segments.

摘要翻译： 操作能够以基本上相同的蚀刻速率蚀刻具有不同图案密度的衬底的不同衬底蚀刻区域的装置的方法。 该装置包括（a）室; （b）室中的阳极和阴极; 和（c）耦合到所述阴极的偏置功率系统，其中所述阴极包括多个阴极段。 操作方法如下。 要蚀刻的衬底放置在阳极和阴极之间，其中衬底包括N个衬底蚀刻区域，并且N个衬底蚀刻区域直接在N个阴极段上方。 确定N偏置功率，当在衬底的蚀刻期间施加到N个阴极段时，将产生对于N个衬底蚀刻区域基本上相同的蚀刻速率。 然后，使用偏置功率系统对N个阴极段施加N个偏置功率。

公开(公告)号：US20060191638A1

公开(公告)日：2006-08-31

申请号：US10906627

申请日：2005-02-28

申请人： Timothy Dalton ,  Emily Gallagher ,  Louis Kindt ,  Carey Thiel ,  Andrew Watts

发明人： Timothy Dalton ,  Emily Gallagher ,  Louis Kindt ,  Carey Thiel ,  Andrew Watts

IPC分类号： C23F1/00 ,  C23C16/00

CPC分类号： H01J37/32706 ,  H01J37/32091 ,  H01J37/32541

摘要： An apparatus (and method for operating the same) which allows etching different substrate etch areas of a substrate having different pattern densities at essentially the same etch rate. The apparatus includes (a) a chamber; (b) an anode and a cathode in the chamber; and (c) a bias power system coupled to the cathode, wherein the cathode includes multiple cathode segments. The operation method includes the steps of: (i) placing a substrate to be etched between the anode and cathode, wherein the substrate includes N substrate etch areas, and the N substrate etch areas are directly above the N cathode segments; (ii) determining N bias powers which, when being applied to the N cathode segments during an etching of the substrate, will result in essentially a same etch rate for the N substrate etch areas; and (iii) using the bias power system to apply the N bias powers the N cathode segments.

摘要翻译： 一种用于以基本上相同的蚀刻速率蚀刻具有不同图案密度的衬底的不同衬底蚀刻区域的装置（及其操作方法）。 该装置包括（a）室; （b）室中的阳极和阴极; 和（c）耦合到所述阴极的偏置功率系统，其中所述阴极包括多个阴极段。 操作方法包括以下步骤：（i）将待蚀刻的衬底放置在阳极和阴极之间，其中衬底包括N个衬底蚀刻区域，并且N个衬底蚀刻区域直接在N个阴极段的上方; （ii）确定N偏压功率，当在衬底的蚀刻期间施加到N个阴极段时，将产生对于N个衬底蚀刻区域基本上相同的蚀刻速率; 和（iii）使用偏置电力系统对N个阴极段施加N个偏置功率。

公开(公告)号：US20050243452A1

公开(公告)日：2005-11-03

申请号：US10709326

申请日：2004-04-28

申请人： Emily Gallagher ,  Rogert Leidy ,  Michael Lercel ,  Kenneth Racette ,  Andrew Watts

发明人： Emily Gallagher ,  Rogert Leidy ,  Michael Lercel ,  Kenneth Racette ,  Andrew Watts

IPC分类号： G03F1/14 ,  G02B5/22 ,  G03F7/00 ,  G03F7/20

CPC分类号： G03F1/64 ,  G03F1/62 ,  G03F7/70983

摘要： A monolithic optical pellicle and method of making used to protect a photomask during photolithography processing. The monolithic optical pellicle is comprised of a pellicle plate having a recessed central portion integrally formed with a perimeter frame of the pellicle plate such that it is a one-piece optical pellicle. The monolithic optical pellicle comprises a material of sufficient rigidity to minimize distortions in and maximize durability of the pellicle when used in combination with the recessed portion having a thickness that prevents sagging thereof due to applied forces on the resultant monolithic optical pellicle. This recessed central portion is the optical pellicle portion of the present monolithic optical pellicle, while the integral perimeter frame is used to attach the monolithic optical pellicle at the desired stand-off distance to a photomask. The monolithic optical pellicle preferably comprises a material that is transparent to an exposure field at about 157 nm wavelengths.

摘要翻译： 一种单片光学防护薄膜和用于在光刻处理期间保护光掩模的方法。 单片光学防护薄膜组件由具有与防护薄膜组件的周边框架一体形成的凹形中心部分的防护薄膜组成，使得它是一体的光学防护薄片组件。 单片光学防护薄膜组件包括足够刚度的材料，以最小化防护薄膜组件的失真并最大化耐久性的材料，当与具有防止由于所得单片光学防护薄膜组件上施加的力而下垂的凹陷部分组合时。 这个凹陷的中心部分是本单片光学防护薄膜的光学防护薄膜部分，而整体的周边框架用于以一个光掩模的所需的间隔距离连接单片光学薄膜。 单片光学防护薄膜优选包括对于约157nm波长的曝光场透明的材料。

公开(公告)号：US08082255B1

公开(公告)日：2011-12-20

申请号：US12623065

申请日：2009-11-20

申请人： Edward J. Carlson, Jr. ,  Andrew Watts ,  Steve Jernigan ,  Robert Hubbard ,  Ferol Vernon

发明人： Edward J. Carlson, Jr. ,  Andrew Watts ,  Steve Jernigan ,  Robert Hubbard ,  Ferol Vernon

IPC分类号： G06F17/30

CPC分类号： G06Q10/087 ,  G06Q30/0601 ,  G06Q30/0621 ,  Y10S707/913 ,  Y10S707/966

摘要： A process for creating a melded visual image to accompany a delivery of digital content. The melded image including at least a digital image associated with the digital content and a first placement image. The first placement image selected for delivery with the digital image in accordance with the execution of one or more rules concerning the digital content or the end user receiving the digital content. The melded image may contain constituent parts that have been altered such as changing the aspect ratio or transparency so that the digital image and the placement image can be displayed on a display screen associated with at least one class of player device that may play the digital content. The placement image may be part of an advertising campaign.

摘要翻译： 用于创建融合的视觉图像以伴随数字内容的传送的过程。 所述熔接图像至少包括与所述数字内容相关联的数字图像和第一放置图像。 根据关于数字内容的一个或多个规则的执行或接收数字内容的最终用户，选择用于与数字图像一起传送的第一放置图像。 熔融图像可以包含已经被改变的组成部分，例如改变长宽比或透明度，使得数字图像和放置图像可以显示在与可以播放数字内容的至少一类播放器设备相关联的显示屏幕上 。 展示位置图片可能是广告系列的一部分。

公开(公告)号：US20060019412A1

公开(公告)日：2006-01-26

申请号：US10710602

申请日：2004-07-23

申请人： Jed Rankin ,  Andrew Watts

发明人： Jed Rankin ,  Andrew Watts

IPC分类号： H01L21/66

CPC分类号： G03F7/203 ,  G03F7/70425 ,  G03F7/7045 ,  G03F7/70608 ,  G03F7/70625

摘要： A method to correct critical dimension errors during a semiconductor manufacturing process. The method includes providing a first semiconductor device. The first semiconductor device is analyzed to determine at least one critical dimension error within the first semiconductor device. A dose of electron beam exposure to correct the at least one critical dimension error during a subsequent process to form a second semiconductor device, or during modification of the first semiconductor device is determined. The subsequent process comprises providing a semiconductor structure. The semiconductor structure comprises a photoresist layer on a semiconductor substrate. A plurality of features are formed in the photoresist layer. At least one feature of the plurality of features comprises the at least one critical dimension error. The at least one feature comprising the critical dimension error is corrected by exposing the at least one feature to an electron beam comprising the dose of electron beam exposure, resulting in reduction of the size, or shrinkage, of the at least one feature comprising a critical dimension error.

摘要翻译： 一种在半导体制造过程中校正关键尺寸误差的方法。 该方法包括提供第一半导体器件。 分析第一半导体器件以确定第一半导体器件内的至少一个临界尺寸误差。 确定在后续处理中形成第二半导体器件或在修改第一半导体器件期间校正至少一个临界尺寸误差的电子束曝光剂量。 随后的工艺包括提供半导体结构。 半导体结构包括半导体衬底上的光致抗蚀剂层。 在光致抗蚀剂层中形成多个特征。 多个特征中的至少一个特征包括至少一个临界尺寸误差。 包括临界尺寸误差的至少一个特征通过将至少一个特征暴露于包括电子束暴露的剂量的电子束来校正，导致包括关键的至少一个特征的至少一个特征的尺寸或收缩的减小 尺寸误差。

公开(公告)号：US20100228974A1

公开(公告)日：2010-09-09

申请号：US12396505

申请日：2009-03-03

申请人： Andrew Watts ,  Bruce W. Yancy

发明人： Andrew Watts ,  Bruce W. Yancy

IPC分类号： H04L9/32 ,  H04L12/28

CPC分类号： H04L12/4666 ,  H04L12/4633 ,  H04L63/0272 ,  H04L63/164 ,  H04L69/22

摘要： In accordance with a nonlimiting example, a network device transfers communications data along a communications channel within an Internet Protocol (IP) network. A communications module includes a signal input connected to the communications channel of the IP network and receives an Ethernet packet having an Ethernet header and IP data. A processor is coupled to the communications module and processes the Ethernet packet. It removes the Ethernet header and adds Virtual Local Area Network (VLAN) tagging information to a padding section in the packet. In one aspect, the processor includes an encryption module that encrypts the VLAN tagging information along with the IP data. The network device includes a signal output through which the packet is transferred to a destination within the IP network over the communications channel as an IPSec tunnel.

摘要翻译： 根据非限制性示例，网络设备沿着因特网协议（IP）网络内的通信信道传送通信数据。 通信模块包括连接到IP网络的通信信道的信号输入，并且接收具有以太网报头和IP数据的以太网分组。 处理器耦合到通信模块并处理以太网分组。 它删除以太网头，并将虚拟局域网（VLAN）标记信息添加到数据包中的填充部分。 一方面，处理器包括加密模块，其与IP数据一起加密VLAN标签信息。 网络设备包括信号输出，通过该信号输出通过通信信道将分组传送到IP网络内的目的地作为IPSec隧道。

公开(公告)号：US20070282103A1

公开(公告)日：2007-12-06

申请号：US10581143

申请日：2004-12-02

申请人： Michael Butters ,  Richard Wisedale ,  Mathew Welham ,  Colin Thomson ,  Andrew Watts

发明人： Michael Butters ,  Richard Wisedale ,  Mathew Welham ,  Colin Thomson ,  Andrew Watts

IPC分类号： C07D239/00

CPC分类号： C07D497/04 ,  C07D513/04

摘要： A method for the preparation of a compound of formula (I) or a pharmaceutically acceptable salt or solvate thereof; from a compound of the formula: (IV); wherein L represents a leaving group.

摘要翻译： 一种制备式（I）化合物或其药学上可接受的盐或溶剂合物的方法; 由式（IV）表示的化合物： 其中L表示离去基团。

公开(公告)号：US08181009B2

公开(公告)日：2012-05-15

申请号：US12396505

申请日：2009-03-03

申请人： Andrew Watts ,  Bruce W. Yancy

发明人： Andrew Watts ,  Bruce W. Yancy

IPC分类号： H04L29/06

CPC分类号： H04L12/4666 ,  H04L12/4633 ,  H04L63/0272 ,  H04L63/164 ,  H04L69/22

摘要： In accordance with a nonlimiting example, a network device transfers communications data along a communications channel within an Internet Protocol (IP) network. A communications module includes a signal input connected to the communications channel of the IP network and receives an Ethernet packet having an Ethernet header and IP data. A processor is coupled to the communications module and processes the Ethernet packet. It removes the Ethernet header and adds Virtual Local Area Network (VLAN) tagging information to a padding section in the packet. In one aspect, the processor includes an encryption module that encrypts the VLAN tagging information along with the IP data. The network device includes a signal output through which the packet is transferred to a destination within the IP network over the communications channel as an IPSec tunnel.

摘要翻译： 根据非限制性示例，网络设备沿着因特网协议（IP）网络内的通信信道传送通信数据。 通信模块包括连接到IP网络的通信信道的信号输入，并且接收具有以太网报头和IP数据的以太网分组。 处理器耦合到通信模块并处理以太网分组。 它删除以太网头，并将虚拟局域网（VLAN）标记信息添加到数据包中的填充部分。 一方面，处理器包括加密模块，其与IP数据一起加密VLAN标签信息。 网络设备包括信号输出，通过该信号输出通过通信信道将分组传送到IP网络内的目的地作为IPSec隧道。

公开(公告)号：US20090043097A1

公开(公告)日：2009-02-12

申请号：US12121228

申请日：2008-05-15

申请人： Colin Thomson ,  Andrew Watts ,  Michael Butters ,  Matthew James Welham ,  Richard Wisedale

发明人： Colin Thomson ,  Andrew Watts ,  Michael Butters ,  Matthew James Welham ,  Richard Wisedale

IPC分类号： C07D513/04

CPC分类号： C07D497/04 ,  C07D513/04

摘要： A method for the preparation of a compound of formula (1) or a pharmaceutically acceptable salt or solvate thereof; from a compound of the formula: (IV); wherein L represents a leaving group.

摘要翻译： 一种制备式（1）化合物或其药学上可接受的盐或溶剂合物的方法; 由式（IV）表示的化合物： 其中L表示离去基团。

公开(公告)号：US20050170261A1

公开(公告)日：2005-08-04

申请号：US10708010

申请日：2004-02-02

申请人： Andrew Watts

发明人： Andrew Watts

IPC分类号： G03C5/00 ,  G03F1/00 ,  G03F9/00

CPC分类号： G03F1/32

摘要： A method of making an embedded attenuated phase shift mask (EAPSM) comprises initially providing a phase shift mask substrate having a layer of phase shifting material and a layer of an opaque material, and depositing a first resist layer on the substrate. The first resist layer is exposed by a direct write electron beam or laser energy source and developed, and the substrate is etched, to create first level phase shifting image segments on the substrate corresponding to areas of critical structures to be exposed with the EAPSM. The method then includes depositing a second resist layer on the substrate. Using a single frame exposure mask corresponding to non-critical areas outside the critical structure areas, the second resist layer is then exposed by simultaneous projection exposure. The method then includes developing the second resist layer and etching the substrate to remove the opaque material from the critical structure areas.

摘要翻译： 制造嵌入式衰减相移掩模（EAPSM）的方法包括：首先提供具有相移材料层和不透明材料层的相移掩模衬底，以及在衬底上沉积第一抗蚀剂层。 第一抗蚀剂层通过直接写入电子束或激光能量源曝光并显影，并且蚀刻衬底，以在衬底上形成对应于要与EAPSM一起曝光的关键结构区域的第一级移相图像段。 该方法然后包括在衬底上沉积第二抗蚀剂层。 使用对应于临界结构区域之外的非关键区域的单个帧曝光掩模，然后通过同时投影曝光来曝光第二抗蚀剂层。 该方法然后包括显影第二抗蚀剂层并蚀刻基底以从关键结构区域去除不透明材料。