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公开(公告)号：US20090204769A1
公开(公告)日：2009-08-13
申请号：US12028196
申请日：2008-02-08
IPC分类号： G06F12/00
CPC分类号： G06F12/0888 , G06F12/0897 , G06F12/1009
摘要： Embodiments of the invention provide methods and apparatus for selectively bypassing cache levels when processing non-reusable transient data in a cache coherent system. To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit “bypass type” field among other attribute bits that index which bits of a Special Purpose Register (SPR) identify the cache levels to be bypassed.
摘要翻译： 本发明的实施例提供了当在高速缓存一致性系统中处理不可重用瞬态数据时选择性地绕过高速缓存级别的方法和装置。 为了选择性地绕过高速缓存级别，可以采用页表项（PTE）机制。 为了限制PTE位的数量，PTE可能具有其他属性位中的2位“旁路类型”字段，这些位指定特殊用途寄存器（SPR）的哪些位标识要旁路的高速缓存级别。
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公开(公告)号：US08108617B2
公开(公告)日：2012-01-31
申请号：US12028196
申请日：2008-02-08
IPC分类号： G06F12/12
CPC分类号： G06F12/0888 , G06F12/0897 , G06F12/1009
摘要： Embodiments of the invention provide methods and apparatus for selectively bypassing cache levels when processing non-reusable transient data in a cache coherent system. To selectively bypass cache levels a page table entry (PTE) mechanism may be employed. To limit the number of PTE bits, the PTE may have a 2-bit “bypass type” field among other attribute bits that index which bits of a Special Purpose Register (SPR) identify the cache levels to be bypassed.
摘要翻译： 本发明的实施例提供了当在高速缓存一致性系统中处理不可重用瞬态数据时选择性地绕过高速缓存级别的方法和装置。 为了选择性地绕过高速缓存级别，可以采用页表项（PTE）机制。 为了限制PTE位的数量，PTE可能具有其他属性位中的2位“旁路类型”字段，这些位指定特殊用途寄存器（SPR）的哪些位标识要旁路的高速缓存级别。
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公开(公告)号：US20100058026A1
公开(公告)日：2010-03-04
申请号：US12548213
申请日：2009-08-26
申请人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
发明人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
IPC分类号： G06F12/06
CPC分类号： G06F12/1027 , G06F12/1009
摘要： An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given virtual address is found in the TLB, the TLB is checked for an indirect TLB entry associated with the given virtual address. Each indirect TLB entry provides the real address of a page table associated with a specified range of virtual addresses and comprises an array of page table entries. If an indirect TLB entry associated with the given virtual address is found in the TLB, a computed address is generated by combining a real address field from the indirect TLB entry and bits from the given virtual address, a page table entry (PTE) is obtained by reading a word from a memory at the computed address, and the PTE is loaded into the TLB as a direct TLB entry.
摘要翻译： 一种用于通过间接TLB条目在硬件中将条目加载到翻译后备缓冲器（TLB）中的增强机制。 在一个实施例中，如果在TLB中没有找到与给定虚拟地址相关联的直接TLB条目，则检查TLB与给定虚拟地址相关联的间接TLB条目。 每个间接TLB条目提供与指定范围的虚拟地址相关联的页表的真实地址，并且包括页表条目数组。 如果在TLB中找到与给定虚拟地址相关联的间接TLB条目，则通过组合来自间接TLB条目的实际地址字段和来自给定虚拟地址的比特来产生计算的地址，获得页表条目（PTE） 通过从所计算的地址的存储器读取一个字，并且将PTE作为直接TLB条目加载到TLB中。
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公开(公告)号：US08296547B2
公开(公告)日：2012-10-23
申请号：US12548213
申请日：2009-08-26
申请人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
发明人： Timothy H. Heil , Benjamin Herrenschmidt , Jon K. Kriegel , Paul Mackerras , Andrew H. Wottreng
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/1009
摘要： An enhanced mechanism for loading entries into a translation lookaside buffer (TLB) in hardware via indirect TLB entries. In one embodiment, if no direct TLB entry associated with the given virtual address is found in the TLB, the TLB is checked for an indirect TLB entry associated with the given virtual address. Each indirect TLB entry provides the real address of a page table associated with a specified range of virtual addresses and comprises an array of page table entries. If an indirect TLB entry associated with the given virtual address is found in the TLB, a computed address is generated by combining a real address field from the indirect TLB entry and bits from the given virtual address, a page table entry (PTE) is obtained by reading a word from a memory at the computed address, and the PTE is loaded into the TLB as a direct TLB entry.
摘要翻译： 一种用于通过间接TLB条目在硬件中将条目加载到翻译后备缓冲器（TLB）中的增强机制。 在一个实施例中，如果在TLB中没有找到与给定虚拟地址相关联的直接TLB条目，则检查TLB与给定虚拟地址相关联的间接TLB条目。 每个间接TLB条目提供与指定范围的虚拟地址相关联的页表的真实地址，并且包括页表条目数组。 如果在TLB中找到与给定虚拟地址相关联的间接TLB条目，则通过组合来自间接TLB条目的实际地址字段和来自给定虚拟地址的比特来产生计算的地址，获得页表条目（PTE） 通过从所计算的地址的存储器读取一个字，并且将PTE作为直接TLB条目加载到TLB中。
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公开(公告)号：US08572325B2
公开(公告)日：2013-10-29
申请号：US12961798
申请日：2010-12-07
IPC分类号： G06F12/08
CPC分类号： G06F12/0871 , G06F2212/282
摘要： Embodiments of the invention are directed to optimizing the performance of a split disk cache. In one embodiment, a disk cache includes a primary region having a read portion and write portion and one or more smaller, sample regions also including a read portion and a write portion. The primary region and one or more sample region each have an independently adjustable ratio of a read portion to a write portion. Cached reads are distributed among the read portions of the primary and sample region, while cached writes are distributed among the write portions of the primary and sample region. The performance of the primary region and the performance of the sample region are tracked, such as by obtaining a hit rate for each region during a predefined interval. The read/write ratio of the primary region is then selectively adjusted according to the performance of the one or more sample regions.
摘要翻译： 本发明的实施例旨在优化分割盘高速缓存的性能。 在一个实施例中，磁盘高速缓存包括具有读取部分和写入部分的主区域以及还包括读取部分和写入部分的一个或多个更小的采样区域。 主区域和一个或多个采样区域各自具有读取部分与写入部分的独立可调比率。 高速缓存的读取分布在主要和采样区域的读取部分之间，而高速缓存的写入分布在主要和样本区域的写入部分之间。 跟踪主区域的性能和样本区域的性能，例如通过在预定义的间隔期间获得每个区域的命中率。 然后根据一个或多个样品区域的性能选择性地调节主区域的读/写比。
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公开(公告)号：US08423715B2
公开(公告)日：2013-04-16
申请号：US12113286
申请日：2008-05-01
申请人： Timothy H. Heil , Robert A. Shearer
发明人： Timothy H. Heil , Robert A. Shearer
IPC分类号： G06F12/08
CPC分类号： G06F12/122 , G06F12/128
摘要： A memory hierarchy in a computer includes levels of cache. The computer also includes a processor operatively coupled through two or more levels of cache to a main random access memory. Caches closer to the processor in the hierarchy are characterized as higher in the hierarchy. Memory management among the levels of cache includes identifying a line in a first cache that is preferably retained in the first cache, where the first cache is backed up by at least one cache lower in the memory hierarchy and the lower cache implements an LRU-type cache line replacement policy. Memory management also includes updating LRU information for the lower cache to indicate that the line has been recently accessed.
摘要翻译： 计算机中的存储器层次结构包括缓存级别。 计算机还包括可操作地通过两个或更多级别的缓存到主随机存取存储器的处理器。 在层次结构中靠近处理器的缓存的特征在于层次结构中较高。 缓存级别之间的存储器管理包括识别优选地保留在第一高速缓存中的第一高速缓存中的行，其中第一高速缓存由存储器层级中的至少一个高速缓存备份，下级高速缓存实现LRU类型 缓存行替换策略。 内存管理还包括更新低级缓存的LRU信息，以指示行最近被访问。
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公开(公告)号：US20120203761A1
公开(公告)日：2012-08-09
申请号：US13022850
申请日：2011-02-08
IPC分类号： G06F17/30
CPC分类号： G06F17/30985 , G06K9/00986
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译： 模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。 使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。 在输入流中要搜索的模式由用户定义为一组正则表达式。 要搜索的模式分组在模式上下文集中。 编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。 该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。 对于每个输入字符，PMA执行搜索并返回搜索结果。
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8.发明申请SOFTWARE AND HARDWARE MANAGED DUAL RULE BANK CACHE FOR USE IN A PATTERN MATCHING ACCELERATOR 有权软件和硬件管理的双规则银行卡用于模式匹配加速器公开(公告)号：US20120203970A1
公开(公告)日：2012-08-09
申请号：US13023058
申请日：2011-02-08
IPC分类号： G06F12/08
CPC分类号： G06F17/30985
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译： 模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。 使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。 在输入流中要搜索的模式由用户定义为一组正则表达式。 要搜索的模式分组在模式上下文集中。 编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。 该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。 对于每个输入字符，PMA执行搜索并返回搜索结果。
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9.发明申请公开(公告)号：US20120203755A1
公开(公告)日：2012-08-09
申请号：US13022938
申请日：2011-02-08
IPC分类号： G06F17/30
CPC分类号： G06F17/30985
摘要： A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
摘要翻译： 模式匹配加速器（PMA），用于帮助软件线程查找匹配给定模式的输入数据流中字符串的存在和位置。 使用正则表达式定义模式，该正则表达式被编译成由PMA随后处理的规则组成的数据结构。 在输入流中要搜索的模式由用户定义为一组正则表达式。 要搜索的模式分组在模式上下文集中。 编译定义模式上下文集的正则表达式集合，以生成PMA硬件使用的规则结构。 该规则在搜索运行时间之前被编译并存储在主存储器中，在PMA内的规则高速缓冲存储器中或其组合中。 对于每个输入字符，PMA执行搜索并返回搜索结果。
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公开(公告)号：US20120144109A1
公开(公告)日：2012-06-07
申请号：US12961798
申请日：2010-12-07
CPC分类号： G06F12/0871 , G06F2212/282
摘要： Embodiments of the invention are directed to optimizing the performance of a split disk cache. In one embodiment, a disk cache includes a primary region having a read portion and write portion and one or more smaller, sample regions also including a read portion and a write portion. The primary region and one or more sample region each have an independently adjustable ratio of a read portion to a write portion. Cached reads are distributed among the read portions of the primary and sample region, while cached writes are distributed among the write portions of the primary and sample region. The performance of the primary region and the performance of the sample region are tracked, such as by obtaining a hit rate for each region during a predefined interval. The read/write ratio of the primary region is then selectively adjusted according to the performance of the one or more sample regions.
摘要翻译： 本发明的实施例涉及优化分割盘高速缓存的性能。 在一个实施例中，磁盘高速缓存包括具有读取部分和写入部分的主区域以及还包括读取部分和写入部分的一个或多个更小的采样区域。 主区域和一个或多个采样区域各自具有读取部分与写入部分的独立可调比率。 高速缓存的读取分布在主要和采样区域的读取部分之间，而高速缓存的写入分布在主要和样本区域的写入部分之间。 跟踪主区域的性能和样本区域的性能，例如通过在预定义的间隔期间获得每个区域的命中率。 然后根据一个或多个样品区域的性能选择性地调节主区域的读/写比。
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